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From: Pu Wen <puwen@hygon.cn>
To: boris.ostrovsky@oracle.com, jgross@suse.com, bp@alien8.de,
	tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, thomas.lendacky@amd.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	xen-devel@lists.xenproject.org, Pu Wen <puwen@hygon.cn>
Subject: [PATCH v8 12/16] x86/xen: Add Hygon Dhyana support to Xen
Date: Sun, 23 Sep 2018 17:36:46 +0800	[thread overview]
Message-ID: <311bf41f08f24550aa6c5da3f1e03a68d3b89dac.1537533369.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1537533368.git.puwen@hygon.cn>

To make Xen works functionally on Hygon platform, reuse AMD's Xen
support code path for Hygon Dhyana CPU.

There are six core performance events counters per thread, so there are
six MSRs for these counters(0-5). Also there are four legacy PMC MSRs,
they are alias of the counters(0-3).

In this version of kernel Hygon use the legacy and safe version of MSR
access. It works fine when VPMU enabled in Xen on Hygon platform by
testing with perf.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
 arch/x86/xen/pmu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index 7d00d4a..9403854 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
 			k7_counters_mirrored = 0;
 			break;
 		}
+	} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+		amd_num_counters = F10H_NUM_COUNTERS;
+		amd_counters_base = MSR_K7_PERFCTR0;
+		amd_ctrls_base = MSR_K7_EVNTSEL0;
+		amd_msr_step = 1;
+		k7_counters_mirrored = 0;
 	} else {
 		uint32_t eax, ebx, ecx, edx;
 
@@ -285,7 +291,7 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
 
 bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
 {
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
 		if (is_amd_pmu_msr(msr)) {
 			if (!xen_amd_pmu_emulate(msr, val, 1))
 				*val = native_read_msr_safe(msr, err);
@@ -308,7 +314,7 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
 {
 	uint64_t val = ((uint64_t)high << 32) | low;
 
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
 		if (is_amd_pmu_msr(msr)) {
 			if (!xen_amd_pmu_emulate(msr, &val, 0))
 				*err = native_write_msr_safe(msr, low, high);
@@ -379,7 +385,7 @@ static unsigned long long xen_intel_read_pmc(int counter)
 
 unsigned long long xen_read_pmc(int counter)
 {
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 		return xen_amd_read_pmc(counter);
 	else
 		return xen_intel_read_pmc(counter);
-- 
2.7.4

  parent reply	other threads:[~2018-09-23  9:36 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-23  9:30 [PATCH v8 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-09-23  9:30 ` Pu Wen
2018-09-23  9:33 ` [PATCH v8 01/16] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2018-09-23  9:33   ` Pu Wen
2018-09-23  9:33 ` [PATCH v8 02/16] x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana Pu Wen
2018-09-23  9:33   ` Pu Wen
2018-09-23  9:34 ` [PATCH v8 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Pu Wen
2018-09-23  9:34   ` Pu Wen
2018-09-23  9:34 ` [PATCH v8 04/16] x86/smpboot: SMP init no delay and not flush caches before sleep Pu Wen
2018-09-23  9:34   ` Pu Wen
2018-09-23  9:34 ` [PATCH v8 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure Pu Wen
2018-09-23  9:34   ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 06/16] x86/alternative: Init ideal_nops for Hygon Dhyana Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 07/16] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23 11:10   ` Borislav Petkov
2018-09-23 11:10     ` Borislav Petkov
2018-09-23 12:54     ` Pu Wen
2018-09-23 12:54       ` Pu Wen
2018-09-24 15:24   ` Borislav Petkov
2018-09-24 15:24     ` Borislav Petkov
2018-09-25 12:27     ` Pu Wen
2018-09-25 12:27       ` Pu Wen
2018-09-25 12:30       ` Borislav Petkov
2018-09-25 12:30         ` Borislav Petkov
2018-09-25 12:57         ` Pu Wen
2018-09-25 12:57           ` Pu Wen
2018-09-25 14:45     ` [PATCH 1/2] x86/amd_nb: Add vendor checking for strict function access Pu Wen
2018-09-25 14:45       ` Pu Wen
2018-09-25 14:46     ` [PATCH 2/2] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-25 14:46       ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 08/16] x86/apic: Add Hygon Dhyana support to APIC Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 09/16] x86/bugs: Add mitigation to spectre and no meltdown for Hygon Dhyana Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:36 ` [PATCH v8 10/16] x86/mce: Add Hygon Dhyana support to MCE infrastructure Pu Wen
2018-09-23  9:36   ` Pu Wen
2018-09-23  9:36 ` [PATCH v8 11/16] x86/kvm: Add Hygon Dhyana support to KVM infrastructure Pu Wen
2018-09-23  9:36   ` Pu Wen
2018-09-23  9:36 ` Pu Wen [this message]
2018-09-23  9:36   ` [PATCH v8 12/16] x86/xen: Add Hygon Dhyana support to Xen Pu Wen
2018-09-23  9:37 ` [PATCH v8 13/16] ACPI, x86: Add Hygon Dhyana support Pu Wen
2018-09-23  9:37   ` Pu Wen
2018-09-23  9:37 ` [PATCH v8 14/16] cpufreq, " Pu Wen
2018-09-23  9:37   ` Pu Wen
2018-09-23  9:37 ` [PATCH v8 15/16] EDAC, amd64: " Pu Wen
2018-09-23  9:37   ` Pu Wen

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