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From: Pu Wen <puwen@hygon.cn>
To: bp@alien8.de, tglx@linutronix.de, mingo@redhat.com,
	hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	Pu Wen <puwen@hygon.cn>
Subject: [PATCH v8 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure
Date: Sun, 23 Sep 2018 17:34:47 +0800
Message-ID: <9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1537533368.git.puwen@hygon.cn>

The PMU architecture for Hygon Dhyana CPU is similar to the AMD Family
17h one. To support Hygon Dhyana PMU, call amd_pmu_init() to share
AMD PMU initialization flow, and change the PMU name to "HYGON".

The Hygon Dhyana CPU supports both legacy and extension PMC MSRs(perf
counter registers and event selection registers), so add Hygon Dhyana
support in the similar way as AMD does.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Reviewed-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/events/amd/core.c             |  4 ++++
 arch/x86/events/amd/uncore.c           | 20 +++++++++++++-------
 arch/x86/events/core.c                 |  4 ++++
 arch/x86/kernel/cpu/perfctr-watchdog.c |  2 ++
 4 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index c84584b..7d2d7c8 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -669,6 +669,10 @@ static int __init amd_core_pmu_init(void)
 		 * We fallback to using default amd_get_event_constraints.
 		 */
 		break;
+	case 0x18:
+		pr_cont("Fam18h ");
+		/* Using default amd_get_event_constraints. */
+		break;
 	default:
 		pr_err("core perfctr but no constraints; unknown hardware!\n");
 		return -ENODEV;
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 981ba5e..c7d745b 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -507,17 +507,19 @@ static int __init amd_uncore_init(void)
 {
 	int ret = -ENODEV;
 
-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 		return -ENODEV;
 
 	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 		return -ENODEV;
 
-	if (boot_cpu_data.x86 == 0x17) {
+	if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 		/*
-		 * For F17h, the Northbridge counters are repurposed as Data
-		 * Fabric counters. Also, L3 counters are supported too. The PMUs
-		 * are exported based on  family as either L2 or L3 and NB or DF.
+		 * For F17h or F18h, the Northbridge counters are
+		 * repurposed as Data Fabric counters. Also, L3
+		 * counters are supported too. The PMUs are exported
+		 * based on family as either L2 or L3 and NB or DF.
 		 */
 		num_counters_nb		  = NUM_COUNTERS_NB;
 		num_counters_llc	  = NUM_COUNTERS_L3;
@@ -547,7 +549,9 @@ static int __init amd_uncore_init(void)
 		if (ret)
 			goto fail_nb;
 
-		pr_info("AMD NB counters detected\n");
+		pr_info("%s NB counters detected\n",
+			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
+				"HYGON" : "AMD");
 		ret = 0;
 	}
 
@@ -561,7 +565,9 @@ static int __init amd_uncore_init(void)
 		if (ret)
 			goto fail_llc;
 
-		pr_info("AMD LLC counters detected\n");
+		pr_info("%s LLC counters detected\n",
+			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
+				"HYGON" : "AMD");
 		ret = 0;
 	}
 
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index dfb2f7c..9c562f5 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void)
 	case X86_VENDOR_AMD:
 		err = amd_pmu_init();
 		break;
+	case X86_VENDOR_HYGON:
+		err = amd_pmu_init();
+		x86_pmu.name = "HYGON";
+		break;
 	default:
 		err = -ENOTSUPP;
 	}
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index d389083..9556930 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the performance counter register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTR)
 			return (msr - MSR_F15H_PERF_CTR) >> 1;
@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the event selection register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTL)
 			return (msr - MSR_F15H_PERF_CTL) >> 1;
-- 
2.7.4

From: Pu Wen <puwen@hygon.cn>
To: bp@alien8.de, tglx@linutronix.de, mingo@redhat.com,
	hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	Pu Wen <puwen@hygon.cn>
Subject: [PATCH v8 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure
Date: Sun, 23 Sep 2018 17:34:47 +0800
Message-ID: <9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn> (raw)
Message-ID: <20180923093447.ZCue_pIxcBdFlP0G_-BhmLz7PAsD6wdbwDr4gs2ZzAg@z> (raw)
In-Reply-To: <cover.1537533368.git.puwen@hygon.cn>

The PMU architecture for Hygon Dhyana CPU is similar to the AMD Family
17h one. To support Hygon Dhyana PMU, call amd_pmu_init() to share
AMD PMU initialization flow, and change the PMU name to "HYGON".

The Hygon Dhyana CPU supports both legacy and extension PMC MSRs(perf
counter registers and event selection registers), so add Hygon Dhyana
support in the similar way as AMD does.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Reviewed-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/events/amd/core.c             |  4 ++++
 arch/x86/events/amd/uncore.c           | 20 +++++++++++++-------
 arch/x86/events/core.c                 |  4 ++++
 arch/x86/kernel/cpu/perfctr-watchdog.c |  2 ++
 4 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index c84584b..7d2d7c8 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -669,6 +669,10 @@ static int __init amd_core_pmu_init(void)
 		 * We fallback to using default amd_get_event_constraints.
 		 */
 		break;
+	case 0x18:
+		pr_cont("Fam18h ");
+		/* Using default amd_get_event_constraints. */
+		break;
 	default:
 		pr_err("core perfctr but no constraints; unknown hardware!\n");
 		return -ENODEV;
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 981ba5e..c7d745b 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -507,17 +507,19 @@ static int __init amd_uncore_init(void)
 {
 	int ret = -ENODEV;
 
-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 		return -ENODEV;
 
 	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 		return -ENODEV;
 
-	if (boot_cpu_data.x86 == 0x17) {
+	if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 		/*
-		 * For F17h, the Northbridge counters are repurposed as Data
-		 * Fabric counters. Also, L3 counters are supported too. The PMUs
-		 * are exported based on  family as either L2 or L3 and NB or DF.
+		 * For F17h or F18h, the Northbridge counters are
+		 * repurposed as Data Fabric counters. Also, L3
+		 * counters are supported too. The PMUs are exported
+		 * based on family as either L2 or L3 and NB or DF.
 		 */
 		num_counters_nb		  = NUM_COUNTERS_NB;
 		num_counters_llc	  = NUM_COUNTERS_L3;
@@ -547,7 +549,9 @@ static int __init amd_uncore_init(void)
 		if (ret)
 			goto fail_nb;
 
-		pr_info("AMD NB counters detected\n");
+		pr_info("%s NB counters detected\n",
+			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
+				"HYGON" : "AMD");
 		ret = 0;
 	}
 
@@ -561,7 +565,9 @@ static int __init amd_uncore_init(void)
 		if (ret)
 			goto fail_llc;
 
-		pr_info("AMD LLC counters detected\n");
+		pr_info("%s LLC counters detected\n",
+			boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ?
+				"HYGON" : "AMD");
 		ret = 0;
 	}
 
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index dfb2f7c..9c562f5 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void)
 	case X86_VENDOR_AMD:
 		err = amd_pmu_init();
 		break;
+	case X86_VENDOR_HYGON:
+		err = amd_pmu_init();
+		x86_pmu.name = "HYGON";
+		break;
 	default:
 		err = -ENOTSUPP;
 	}
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index d389083..9556930 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -46,6 +46,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the performance counter register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTR)
 			return (msr - MSR_F15H_PERF_CTR) >> 1;
@@ -74,6 +75,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 {
 	/* returns the bit offset of the event selection register */
 	switch (boot_cpu_data.x86_vendor) {
+	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
 		if (msr >= MSR_F15H_PERF_CTL)
 			return (msr - MSR_F15H_PERF_CTL) >> 1;
-- 
2.7.4

  parent reply index

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-23  9:30 [PATCH v8 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-09-23  9:30 ` Pu Wen
2018-09-23  9:33 ` [PATCH v8 01/16] x86/cpu: Create Hygon Dhyana architecture support file Pu Wen
2018-09-23  9:33   ` Pu Wen
2018-09-23  9:33 ` [PATCH v8 02/16] x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana Pu Wen
2018-09-23  9:33   ` Pu Wen
2018-09-23  9:34 ` [PATCH v8 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Pu Wen
2018-09-23  9:34   ` Pu Wen
2018-09-23  9:34 ` [PATCH v8 04/16] x86/smpboot: SMP init no delay and not flush caches before sleep Pu Wen
2018-09-23  9:34   ` Pu Wen
2018-09-23  9:34 ` Pu Wen [this message]
2018-09-23  9:34   ` [PATCH v8 05/16] perf/x86: Add Hygon Dhyana support to PMU infrastructure Pu Wen
2018-09-23  9:35 ` [PATCH v8 06/16] x86/alternative: Init ideal_nops for Hygon Dhyana Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 07/16] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23 11:10   ` Borislav Petkov
2018-09-23 11:10     ` Borislav Petkov
2018-09-23 12:54     ` Pu Wen
2018-09-23 12:54       ` Pu Wen
2018-09-24 15:24   ` Borislav Petkov
2018-09-24 15:24     ` Borislav Petkov
2018-09-25 12:27     ` Pu Wen
2018-09-25 12:27       ` Pu Wen
2018-09-25 12:30       ` Borislav Petkov
2018-09-25 12:30         ` Borislav Petkov
2018-09-25 12:57         ` Pu Wen
2018-09-25 12:57           ` Pu Wen
2018-09-25 14:45     ` [PATCH 1/2] x86/amd_nb: Add vendor checking for strict function access Pu Wen
2018-09-25 14:45       ` Pu Wen
2018-09-25 14:46     ` [PATCH 2/2] x86/pci: Add Hygon Dhyana support to PCI and north bridge Pu Wen
2018-09-25 14:46       ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 08/16] x86/apic: Add Hygon Dhyana support to APIC Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:35 ` [PATCH v8 09/16] x86/bugs: Add mitigation to spectre and no meltdown for Hygon Dhyana Pu Wen
2018-09-23  9:35   ` Pu Wen
2018-09-23  9:36 ` [PATCH v8 10/16] x86/mce: Add Hygon Dhyana support to MCE infrastructure Pu Wen
2018-09-23  9:36   ` Pu Wen
2018-09-23  9:36 ` [PATCH v8 11/16] x86/kvm: Add Hygon Dhyana support to KVM infrastructure Pu Wen
2018-09-23  9:36   ` Pu Wen
2018-09-23  9:36 ` [PATCH v8 12/16] x86/xen: Add Hygon Dhyana support to Xen Pu Wen
2018-09-23  9:36   ` Pu Wen
2018-09-23  9:37 ` [PATCH v8 13/16] ACPI, x86: Add Hygon Dhyana support Pu Wen
2018-09-23  9:37   ` Pu Wen
2018-09-23  9:37 ` [PATCH v8 14/16] cpufreq, " Pu Wen
2018-09-23  9:37   ` Pu Wen
2018-09-23  9:37 ` [PATCH v8 15/16] EDAC, amd64: " Pu Wen
2018-09-23  9:37   ` Pu Wen

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