Re: [PATCH 04/19] LoongArch: Add common headers

[Huacai Chen <chenhuacai@gmail.com>]

Hi, Arnd,

On Fri, Aug 13, 2021 at 5:08 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Fri, Aug 13, 2021 at 10:14 AM Huacai Chen <chenhuacai@gmail.com> wrote:
> > On Fri, Aug 13, 2021 at 3:05 PM Arnd Bergmann <arnd@arndb.de> wrote:
> > >
> > > I still don't see what is special about 40 and 48. From what I can tell,
> > > you have two constraints: the maximum address space size for
> > > the kernel configuration based on the page size and number of
> > > page table levels, and the capabilities of the CPU as described
> > > in the CPUCFG1 register.
> > >
> > > What is the point of introducing an arbitrary third compile-time
> > > limit here rather than calculating it from the page page size?
> >
> > So your problem is why we should provide two configurations VA40 and
> > VA48? This is derived from MIPS of course, but I found that RISC-V and
> > ARM64 also provide VA BITS configuration.
>
> The difference is that on arm64 and riscv, the CONFIG_VA_BITS
> configuration is directly derived from the page table layout.
>
> E.g. when using 16K pages on arm64, you have the choice between
> 47 bits and 36 bits, while your method would apparently force going
> to 40 bits and either waste most of the theoretically available address
> space, or require three-level tables even if you only need 36 bits.
>
After some thinking, I found that ARM64 is "define kernel VABITS
depends on page table layout", and MIPS (also LoongArch) is "define
page table layout depends on kernel VABITS". So you can see:

#ifdef CONFIG_VA_BITS_40
#ifdef CONFIG_PAGE_SIZE_4KB
#define PGD_ORDER               1
#define PUD_ORDER               aieeee_attempt_to_allocate_pud
#define PMD_ORDER               0
#define PTE_ORDER               0
#endif
#ifdef CONFIG_PAGE_SIZE_16KB
#define PGD_ORDER               0
#define PUD_ORDER               aieeee_attempt_to_allocate_pud
#define PMD_ORDER               0
#define PTE_ORDER               0
#endif
#ifdef CONFIG_PAGE_SIZE_64KB
#define PGD_ORDER               0
#define PUD_ORDER               aieeee_attempt_to_allocate_pud
#define PMD_ORDER               aieeee_attempt_to_allocate_pmd
#define PTE_ORDER               0
#endif
#endif

#ifdef CONFIG_VA_BITS_48
#ifdef CONFIG_PAGE_SIZE_4KB
#define PGD_ORDER               0
#define PUD_ORDER               0
#define PMD_ORDER               0
#define PTE_ORDER               0
#endif
#ifdef CONFIG_PAGE_SIZE_16KB
#define PGD_ORDER               1
#define PUD_ORDER               aieeee_attempt_to_allocate_pud
#define PMD_ORDER               0
#define PTE_ORDER               0
#endif
#ifdef CONFIG_PAGE_SIZE_64KB
#define PGD_ORDER               0
#define PUD_ORDER               aieeee_attempt_to_allocate_pud
#define PMD_ORDER               0
#define PTE_ORDER               0
#endif
#endif

Since 40 and 48 is the most popular VABITS of LoongArch hardware, and
LoongArch has a software-managed TLB, it seems "define page table
layout depends on kernel VABITS" is more natural for LoongArch.

Huacai
>         Arnd