From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH V3 06/26] csky: Cache and TLB routines Date: Thu, 6 Sep 2018 16:31:16 +0200 Message-ID: References: <16105a3e54f1c4bb65a5ec81d77af7c176e705c6.1536138304.git.ren_guo@c-sky.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <16105a3e54f1c4bb65a5ec81d77af7c176e705c6.1536138304.git.ren_guo@c-sky.com> Sender: linux-kernel-owner@vger.kernel.org To: Guo Ren Cc: linux-arch , Linux Kernel Mailing List , Thomas Gleixner , Daniel Lezcano , Jason Cooper , c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com, Thomas Petazzoni , wbx@uclibc-ng.org, Greentime Hu List-Id: linux-arch.vger.kernel.org On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h > new file mode 100644 > index 0000000..fcb2142 > --- /dev/null > +++ b/arch/csky/include/asm/io.h > @@ -0,0 +1,23 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. > +#ifndef __ASM_CSKY_IO_H > +#define __ASM_CSKY_IO_H > + > +#include > +#include > +#include > + > +extern void __iomem *ioremap(phys_addr_t offset, size_t size); > + > +extern void iounmap(void *addr); > + > +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, > + size_t size, unsigned long flags); > + > +#define ioremap_nocache(phy, sz) ioremap(phy, sz) > +#define ioremap_wc ioremap_nocache > +#define ioremap_wt ioremap_nocache > + > +#include It is very unusual for an architecture to not need special handling in asm/io.h, to do the proper barriers etc. Can you describe how C-Sky hardware implements MMIO? In particular: - Is a read from uncached memory always serialized with DMA, and with other CPUs doing MMIO access to a different address? - How does endianess work? Are there any buses that flip bytes around when running big-endian, or do you always do that in software? Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-f195.google.com ([209.85.216.195]:34567 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729937AbeIFTHW (ORCPT ); Thu, 6 Sep 2018 15:07:22 -0400 MIME-Version: 1.0 References: <16105a3e54f1c4bb65a5ec81d77af7c176e705c6.1536138304.git.ren_guo@c-sky.com> In-Reply-To: <16105a3e54f1c4bb65a5ec81d77af7c176e705c6.1536138304.git.ren_guo@c-sky.com> From: Arnd Bergmann Date: Thu, 6 Sep 2018 16:31:16 +0200 Message-ID: Subject: Re: [PATCH V3 06/26] csky: Cache and TLB routines Content-Type: text/plain; charset="UTF-8" Sender: linux-arch-owner@vger.kernel.org List-ID: To: Guo Ren Cc: linux-arch , Linux Kernel Mailing List , Thomas Gleixner , Daniel Lezcano , Jason Cooper , c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com, Thomas Petazzoni , wbx@uclibc-ng.org, Greentime Hu Message-ID: <20180906143116.eHu4Qg-LiRdaSKkUrtMsrRbpgpTYz6C-sv0PCUYn5AQ@z> On Wed, Sep 5, 2018 at 2:08 PM Guo Ren wrote: > diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h > new file mode 100644 > index 0000000..fcb2142 > --- /dev/null > +++ b/arch/csky/include/asm/io.h > @@ -0,0 +1,23 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. > +#ifndef __ASM_CSKY_IO_H > +#define __ASM_CSKY_IO_H > + > +#include > +#include > +#include > + > +extern void __iomem *ioremap(phys_addr_t offset, size_t size); > + > +extern void iounmap(void *addr); > + > +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr, > + size_t size, unsigned long flags); > + > +#define ioremap_nocache(phy, sz) ioremap(phy, sz) > +#define ioremap_wc ioremap_nocache > +#define ioremap_wt ioremap_nocache > + > +#include It is very unusual for an architecture to not need special handling in asm/io.h, to do the proper barriers etc. Can you describe how C-Sky hardware implements MMIO? In particular: - Is a read from uncached memory always serialized with DMA, and with other CPUs doing MMIO access to a different address? - How does endianess work? Are there any buses that flip bytes around when running big-endian, or do you always do that in software? Arnd