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Tue, 2 Mar 2021 01:40:37 +0000 From: Michael Kelley To: Daniel Lezcano , Stephen Hemminger , KY Srinivasan , "wei.liu@kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "arnd@arndb.de" , "linux-hyperv@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "linux-arch@vger.kernel.org" Subject: RE: [PATCH v2 10/10] clocksource/drivers/hyper-v: Move handling of STIMER0 interrupts Thread-Topic: [PATCH v2 10/10] clocksource/drivers/hyper-v: Move handling of STIMER0 interrupts Thread-Index: AQHXDjh3b7sfn0hZqU2r+eHOEjUhQKpveW4AgABzygA= Date: Tue, 2 Mar 2021 01:40:37 +0000 Message-ID: References: <1614561332-2523-1-git-send-email-mikelley@microsoft.com> <1614561332-2523-11-git-send-email-mikelley@microsoft.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=true; MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2021-03-02T01:40:36Z; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR21MB1593.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 79c67d5b-ea1d-4c83-33a0-08d8dd1c2e59 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Mar 2021 01:40:37.7676 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /Ia246mVJTCqwiE+8rsPAxn0K85LyQxMryKa/GZZ7+AJ9SRlia5nve9LYwGhpQ85oasdR/6X0rg+xkvXF1FdIk39/jwR96B7IJVIee4jazg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR21MB1579 Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Daniel Lezcano Sent: Monday, March 1, 202= 1 10:45 AM >=20 > On 01/03/2021 02:15, Michael Kelley wrote: > > STIMER0 interrupts are most naturally modeled as per-cpu IRQs. But > > because x86/x64 doesn't have per-cpu IRQs, the core STIMER0 interrupt > > handling machinery is done in code under arch/x86 and Linux IRQs are > > not used. Adding support for ARM64 means adding equivalent code > > using per-cpu IRQs under arch/arm64. > > > > A better model is to treat per-cpu IRQs as the normal path (which it is > > for modern architectures), and the x86/x64 path as the exception. Do th= is > > by incorporating standard Linux per-cpu IRQ allocation into the main > > SITMER0 driver code, and bypass it in the x86/x64 exception case. For > > x86/x64, special case code is retained under arch/x86, but no STIMER0 > > interrupt handling code is needed under arch/arm64. > > > > No functional change. > > > > Signed-off-by: Michael Kelley > > --- > > arch/x86/hyperv/hv_init.c | 2 +- > > arch/x86/include/asm/mshyperv.h | 4 - > > arch/x86/kernel/cpu/mshyperv.c | 10 +-- > > drivers/clocksource/hyperv_timer.c | 180 ++++++++++++++++++++++++++---= -------- > > include/asm-generic/mshyperv.h | 5 -- > > include/clocksource/hyperv_timer.h | 3 +- > > 6 files changed, 132 insertions(+), 72 deletions(-) > > > > diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c > > index 9af4f8a..9d10025 100644 > > --- a/arch/x86/hyperv/hv_init.c > > +++ b/arch/x86/hyperv/hv_init.c > > @@ -327,7 +327,7 @@ static void __init hv_stimer_setup_percpu_clockev(v= oid) > > * Ignore any errors in setting up stimer clockevents > > * as we can run with the LAPIC timer as a fallback. > > */ > > - (void)hv_stimer_alloc(); > > + (void)hv_stimer_alloc(false); > > > > /* > > * Still register the LAPIC timer, because the direct-mode STIMER is > > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/msh= yperv.h > > index 5433312..6d4891b 100644 > > --- a/arch/x86/include/asm/mshyperv.h > > +++ b/arch/x86/include/asm/mshyperv.h > > @@ -31,10 +31,6 @@ static inline u64 hv_get_register(unsigned int reg) > > > > void hyperv_vector_handler(struct pt_regs *regs); > > > > -static inline void hv_enable_stimer0_percpu_irq(int irq) {} > > -static inline void hv_disable_stimer0_percpu_irq(int irq) {} > > - > > - > > #if IS_ENABLED(CONFIG_HYPERV) > > extern int hyperv_init_cpuhp; > > > > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyp= erv.c > > index 41fd84a..cebed53 100644 > > --- a/arch/x86/kernel/cpu/mshyperv.c > > +++ b/arch/x86/kernel/cpu/mshyperv.c > > @@ -90,21 +90,17 @@ void hv_remove_vmbus_handler(void) > > set_irq_regs(old_regs); > > } > > > > -int hv_setup_stimer0_irq(int *irq, int *vector, void (*handler)(void)) > > +/* For x86/x64, override weak placeholders in hyperv_timer.c */ > > +void hv_setup_stimer0_handler(void (*handler)(void)) > > { > > - *vector =3D HYPERV_STIMER0_VECTOR; > > - *irq =3D -1; /* Unused on x86/x64 */ > > hv_stimer0_handler =3D handler; > > - return 0; > > } > > -EXPORT_SYMBOL_GPL(hv_setup_stimer0_irq); > > > > -void hv_remove_stimer0_irq(int irq) > > +void hv_remove_stimer0_handler(void) > > { > > /* We have no way to deallocate the interrupt gate */ > > hv_stimer0_handler =3D NULL; > > } > > -EXPORT_SYMBOL_GPL(hv_remove_stimer0_irq); > > > > void hv_setup_kexec_handler(void (*handler)(void)) > > { > > diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/h= yperv_timer.c > > index cdb8e0c..b2bf5e5 100644 > > --- a/drivers/clocksource/hyperv_timer.c > > +++ b/drivers/clocksource/hyperv_timer.c > > @@ -18,6 +18,9 @@ > > #include > > #include > > #include > > +#include > > +#include > > +#include > > #include > > #include > > #include > > @@ -43,14 +46,13 @@ > > */ > > static bool direct_mode_enabled; > > > > -static int stimer0_irq; > > -static int stimer0_vector; > > +static int stimer0_irq =3D -1; > > +static long __percpu *stimer0_evt; >=20 > Why not >=20 > static DEFINE_PER_CPU(long, stimer0_evt); >=20 > no need of allocation /free ? >=20 Indeed! I'll make that simplification in v3 of the patch set. Michael