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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 35sm2768481pgq.91.2021.06.04.15.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 15:10:25 -0700 (PDT) Date: Fri, 04 Jun 2021 15:10:25 -0700 (PDT) X-Google-Original-Date: Fri, 04 Jun 2021 15:10:24 PDT (-0700) Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support In-Reply-To: CC: guoren@kernel.org, Anup Patel , anup@brainfault.org, drew@beagleboard.org, Christoph Hellwig , wefu@redhat.com, lazyparser@gmail.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev, guoren@linux.alibaba.com, Paul Walmsley From: Palmer Dabbelt To: Arnd Bergmann Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Fri, 04 Jun 2021 14:26:11 PDT (-0700), Arnd Bergmann wrote: > On Fri, Jun 4, 2021 at 6:14 PM Palmer Dabbelt wrote: >> >> To give some common examples that make it break down: >> >> >> >> - 32-bit vs 64-bit already violates that rule on risc-v (as it does on >> >> most other architectures) >> >> Yes, and there's no way around that on RISC-V. They're different base >> ISAs therefor re-define the same instructions, so we're essentially at >> two kernel binaries by that point. The platform spec says rv64gc, so we >> can kind of punt on this one for now. If rv32 hardware shows up >> we'll probably want a standard system there too, which is why we've >> avoided coupling kernel portability to XLEN. > > I would actually put 32-bit into the same category as NOMMU, XIP > and the built-in DTB: > Since it seems unrealistic to expect an rv32 Debian or Fedora build, > there is very little to gain by enforcing compatibility between machines. > This is different from 32-bit Arm, which is widely used across multiple > distros and many SoCs. OK, well, that's what the spec says already. Maybe the right answer is to just add that "be compatible with the platform spec" Kconfig and have it also enforce rv64gc like the spec says. > >> >> - architectures that support both big-endian and little-endian kernels >> >> tend to have platforms that require one or the other (e.g. mips, >> >> though not arm). Not an issue for you. >> >> It is now! We've added big-endian to RISC-V. There's no hardware yet >> and very little software support. IMO the right answer is to ban that >> from the platform spec, but again it'll depnd on what vendors want to >> build (though anyone is listening, please don't make my life miserable >> ;)). > > I don't see any big-endian support in linux-next. This one does seem > worth enforcing to be kept out, as it would double the number of user > space ABIs, not just kernel configurations. On arm64, I think the general > feeling is now that we would have been better off not merging big-endian > support into the kernel as an option, but it still seemed important at the > time. Not that there is anything really wrong with big-endian by itself, > just that there is no use case that is worth the added complexity of > supporting both. > > Let me know if there are patches you want me to Nak in the future ;-) Sorry, by "added big-endian to RISC-V" I meant to the ISA, not to Linux. We haven't had any interesting in adding it to Linux. The interest has all been in the embedded space.