Re: [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform

[John Garry <john.garry@huawei.com>]

>>>>> On Thu, Nov 07, 2019 at 03:56:04PM +0800, Shaokun Zhang wrote:
>>>>>> @@ -338,8 +339,10 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
>>>>>>     /*
>>>>>>      * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
>>>>>> - * If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
>>>>>> - * and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
>>>>>> + * If multi-threading is supported, On Huawei Kunpeng 920 SoC whose cpu
>>>>>> + * core is tsv110, CCL_ID is the low 3-bits in MPIDR[Aff2] and SCCL_ID
>>>>>> + * is the upper 5-bits of Aff2 field; while for other cpu types, SCCL_ID
>>>>>> + * is in MPIDR[Aff3] and CCL_ID is in MPIDR[Aff2], if not, SCCL_ID
>>>>>>      * is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
>>>>>>      */
>>>>>>     static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
>>>>>> @@ -347,12 +350,19 @@ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
>>>>>>     	u64 mpidr = read_cpuid_mpidr();
>>>>>>     	if (mpidr & MPIDR_MT_BITMASK) {
>>>>>> -		int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>>>> -
>>>>>> -		if (sccl_id)
>>>>>> -			*sccl_id = aff2 >> 3;
>>>>>> -		if (ccl_id)
>>>>>> -			*ccl_id = aff2 & 0x7;
>>>>>> +		if (read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
>>>>>> +			int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>>>> +
>>>>>> +			if (sccl_id)
>>>>>> +				*sccl_id = aff2 >> 3;
>>>>>> +			if (ccl_id)
>>>>>> +				*ccl_id = aff2 & 0x7;
>>>>>> +		} else {
>>>>>> +			if (sccl_id)
>>>>>> +				*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
>>>>>> +			if (ccl_id)
>>>>>> +				*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
>>>>>> +		}
>>>>>
>>>>> [I prefer Mark's version, so please reply to indicate whether or not it
>>>>>     works for you]
>>>>
>>>> Replying on Shaokun's behalf as he appears offline now.
>>>>
>>>> In response to "> If TSV110 is always MT, ":
>>>>
>>>> It isn't. There are 2 spins of Huawei Kunpeng 920 SoC which includes
>>>> TaishanV110 aka TSV110: one has the MT bit set and the other without.
>>>
>>> Just to check, for the non-MT variant is the SCCL/CCL assignment
>>> Aff2/Aff1 as with other non-MT parts?
>>
>> We don't support any other non-MT parts for this driver.
> 
> The driver claimed to support non-MT parts before TSV110 came around, so that
> statement confuses me.

A couple of points on this:

- We gave up on upstreaming support in this driver for the predecessor 
SoC, which included an A72. You may remember the infamous djtag bus.

- The wording in the comment "If multi-threading is supported, On Huawei 
Kunpeng 920 SoC " is misleading, as it implies that the part found in 
Huawei Kunpeng 920 is MT, which it isn't always.

> 
> For a non-MT TSV110, is Aff2 the SCCL and Aff1 the CCL? 

Yes,

That's what the
> existing code (and Shaokun's patch) assumed.

well I'm going with that as well. Shaokun can confirm the layout.

> 
> Assuming that is the case, I'd suggest we have the following:
> 
> /*
>   * The Super CPU Cluster (SCCL) and CPU Cluster (CCL) IDs can be
>   * determined from the MPIDR_EL1, but the encoding varies by CPU:
>   *
>   * - For MT variants of TSV110 (e.g. found in Kunpeng 920):

Again, this implies that the part found in Kunpeng 920 is MT, which it 
isn't always.

BTW, As I understand, the MIDR variant bits differ between the 2 revs of 
TSV110, so maybe that is a better method to differentiate, but I don't 
see an API exported for this.

>   *   SCCL is Aff2[7:3], CCL is Aff2[2:0]
>   *
>   * - For other MT parts:
>   *   SCCL is Aff3[7:0], CCL is Aff2[7:0]
>   *
>   * - For non-MT parts:
>   *   SCCL is Aff2[7:0], CCL is Aff1[7:0]
>   */
> static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
> {
> 	u64 mpidr = read_cpuid_mpidr();
> 	int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
> 	int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
> 	int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> 	bool mt = mpdir & MPIDR_MT_BITMASK;
> 	int sccl, ccl;
> 
> 	if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
> 		sccl = aff2 >> 3;
> 		ccl = aff2 & 0x7;
> 	} else if (mt) {
> 		sccl = aff3;
> 		ccl = aff2;
> 	} else {
> 		sccl = aff2;
> 		ccl = aff1;
> 	}
> 
> 	if (scclp)
> 		*scclp = sccl;
> 	if (cclp)
> 		*cclp = ccl;
> }
> 
> Thanks,
> Mark.

Thanks,
John

> .
> 


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