[PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[James Clark]

Hi,

I'm resubmitting this with a few of the changes suggested by Will on V2.

I haven't made any changes regarding the open questions about the
discoverability or saving the new reg and passing to output_sample()
because I think it's best to be consistent with the implementations on
other platforms first. I have explained in more detail on v2 [1].

[1]: https://lore.kernel.org/lkml/5fcf1a6f-c8fb-c296-992e-18aae8874095@arm.com/

=======

Changes since v2:

  * Add definition for PERF_REG_EXTENDED_MASK which is needed for
    PERF_PMU_CAP_EXTENDED_REGS to work properly

  * Simplify changes to enum perf_event_arm_regs

Changes since v1:

  * Add Mark's review tag
  * Clarify in docs that it's the SVE register length
  * Split patchset into kernel side and Perf tool changes

=======

When SVE registers are pushed onto the stack the VG register is required to
unwind because the stack offsets would vary by the SVE register width at the
time when the sample was taken.

These first two patches add support for sampling the VG register to the kernel
and the docs. There is another patchset to add support to userspace perf.

A small change is also required to libunwind or libdw depending on which
unwinder is used, and these will be published later. Without these changes Perf
continues to work with both libraries, although the VG register is still not
used for unwinding. 

Thanks
James

James Clark (2):
  perf: arm64: Add SVE vector granule register to user regs
  arm64/sve: Add Perf extensions documentation

 Documentation/arm64/sve.rst             | 20 +++++++++++++++++
 arch/arm64/include/uapi/asm/perf_regs.h |  7 ++++++
 arch/arm64/kernel/perf_regs.c           | 30 +++++++++++++++++++++++--
 drivers/perf/arm_pmu.c                  |  2 +-
 4 files changed, 56 insertions(+), 3 deletions(-)

-- 
2.28.0


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[PATCH v3 1/2] perf: arm64: Add SVE vector granule register to user regs

[James Clark]

Dwarf based unwinding in a function that pushes SVE registers onto
the stack requires the unwinder to know the length of the SVE register
to calculate the stack offsets correctly. This was added to the Arm
specific Dwarf spec as the VG pseudo register[1].

Add the vector length at position 46 if it's requested by userspace and
SVE is supported. If it's not supported then fail to open the event.

The vector length must be on each sample because it can be changed
at runtime via a prctl or ptrace call. Also by adding it as a register
rather than a separate attribute, minimal changes will be required in an
unwinder that already indexes into the register list.

[1]: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Clark <james.clark@arm.com>
---
 arch/arm64/include/uapi/asm/perf_regs.h |  7 ++++++
 arch/arm64/kernel/perf_regs.c           | 30 +++++++++++++++++++++++--
 drivers/perf/arm_pmu.c                  |  2 +-
 3 files changed, 36 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/uapi/asm/perf_regs.h
index d54daafa89e3..0d4b40c78e47 100644
--- a/arch/arm64/include/uapi/asm/perf_regs.h
+++ b/arch/arm64/include/uapi/asm/perf_regs.h
@@ -37,5 +37,12 @@ enum perf_event_arm_regs {
 	PERF_REG_ARM64_SP,
 	PERF_REG_ARM64_PC,
 	PERF_REG_ARM64_MAX,
+
+	/* Extended/pseudo registers */
+	PERF_REG_ARM64_VG = 46, // SVE Vector Granule
+	PERF_REG_ARM64_EXTENDED_MAX
 };
+
+#define PERF_REG_EXTENDED_MASK	(1ULL << PERF_REG_ARM64_VG)
+
 #endif /* _ASM_ARM64_PERF_REGS_H */
diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c
index f6f58e6265df..b4eece3eb17d 100644
--- a/arch/arm64/kernel/perf_regs.c
+++ b/arch/arm64/kernel/perf_regs.c
@@ -9,9 +9,27 @@
 #include <asm/perf_regs.h>
 #include <asm/ptrace.h>
 
+static u64 perf_ext_regs_value(int idx)
+{
+	switch (idx) {
+	case PERF_REG_ARM64_VG:
+		if (WARN_ON_ONCE(!system_supports_sve()))
+			return 0;
+
+		/*
+		 * Vector granule is current length in bits of SVE registers
+		 * divided by 64.
+		 */
+		return (task_get_sve_vl(current) * 8) / 64;
+	default:
+		WARN_ON_ONCE(true);
+		return 0;
+	}
+}
+
 u64 perf_reg_value(struct pt_regs *regs, int idx)
 {
-	if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM64_MAX))
+	if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM64_EXTENDED_MAX))
 		return 0;
 
 	/*
@@ -51,6 +69,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
 	if ((u32)idx == PERF_REG_ARM64_PC)
 		return regs->pc;
 
+	if ((u32)idx >= PERF_REG_ARM64_MAX)
+		return perf_ext_regs_value(idx);
+
 	return regs->regs[idx];
 }
 
@@ -58,7 +79,12 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
 
 int perf_reg_validate(u64 mask)
 {
-	if (!mask || mask & REG_RESERVED)
+	u64 reserved_mask = REG_RESERVED;
+
+	if (system_supports_sve())
+		reserved_mask &= ~(1ULL << PERF_REG_ARM64_VG);
+
+	if (!mask || mask & reserved_mask)
 		return -EINVAL;
 
 	return 0;
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 59d3980b8ca2..3f07df5a7e95 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -894,7 +894,7 @@ static struct arm_pmu *__armpmu_alloc(gfp_t flags)
 		 * pmu::filter_match callback and pmu::event_init group
 		 * validation).
 		 */
-		.capabilities	= PERF_PMU_CAP_HETEROGENEOUS_CPUS,
+		.capabilities	= PERF_PMU_CAP_HETEROGENEOUS_CPUS | PERF_PMU_CAP_EXTENDED_REGS,
 	};
 
 	pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
-- 
2.28.0


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[PATCH v3 2/2] arm64/sve: Add Perf extensions documentation

[James Clark]

Document that the VG register is available in Perf samples

Signed-off-by: James Clark <james.clark@arm.com>
---
 Documentation/arm64/sve.rst | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
index 93c2c2990584..8955bf1bf757 100644
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -452,6 +452,24 @@ The regset data starts with struct user_sve_header, containing:
 * Modifying the system default vector length does not affect the vector length
   of any existing process or thread that does not make an execve() call.
 
+10.  Perf extensions
+--------------------------------
+
+* The arm64 specific DWARF standard [5] added the VG (Vector Granule) register
+  at index 46. This register is used for DWARF unwinding when variable length
+  SVE registers are pushed onto the stack.
+
+* Its value is equivalent to the current SVE vector length (VL) in bits divided
+  by 64.
+
+* The value is included in Perf samples in the regs[46] field if
+  PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 set.
+
+* The value is the current value at the time the sample was taken, and it can
+  change over time.
+
+* If the system doesn't support SVE when perf_event_open is called with these
+  settings, the event will fail to open.
 
 Appendix A.  SVE programmer's model (informative)
 =================================================
@@ -593,3 +611,5 @@ References
     http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf
     http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
     Procedure Call Standard for the ARM 64-bit Architecture (AArch64)
+
+[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst
-- 
2.28.0


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Re: [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation

[Mark Brown]

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On Thu, Sep 01, 2022 at 02:26:58PM +0100, James Clark wrote:

> Document that the VG register is available in Perf samples

Reviewed-by: Mark Brown <broonie@kernel.org>

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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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Re: [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation

[James Clark]

On 01/09/2022 14:33, Mark Brown wrote:
> On Thu, Sep 01, 2022 at 02:26:58PM +0100, James Clark wrote:
> 
>> Document that the VG register is available in Perf samples
> 
> Reviewed-by: Mark Brown <broonie@kernel.org>

Hi Will/Mark R,

Is this set ok to go into 6.1?

Thanks
James

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[Will Deacon]

On Thu, Sep 01, 2022 at 02:26:56PM +0100, James Clark wrote:
> I'm resubmitting this with a few of the changes suggested by Will on V2.
> 
> I haven't made any changes regarding the open questions about the
> discoverability or saving the new reg and passing to output_sample()
> because I think it's best to be consistent with the implementations on
> other platforms first. I have explained in more detail on v2 [1].
> 
> [1]: https://lore.kernel.org/lkml/5fcf1a6f-c8fb-c296-992e-18aae8874095@arm.com/

Fair enough, I can't argue against being consistent.

Given that this exposes subtle new user ABI, do we have any coverage in
the selftests? If not, please could you add something?

Thanks,

Will

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[James Clark]

On 22/09/2022 15:04, Will Deacon wrote:
> On Thu, Sep 01, 2022 at 02:26:56PM +0100, James Clark wrote:
>> I'm resubmitting this with a few of the changes suggested by Will on V2.
>>
>> I haven't made any changes regarding the open questions about the
>> discoverability or saving the new reg and passing to output_sample()
>> because I think it's best to be consistent with the implementations on
>> other platforms first. I have explained in more detail on v2 [1].
>>
>> [1]: https://lore.kernel.org/lkml/5fcf1a6f-c8fb-c296-992e-18aae8874095@arm.com/
> 
> Fair enough, I can't argue against being consistent.
> 
> Given that this exposes subtle new user ABI, do we have any coverage in
> the selftests? If not, please could you add something?
> 

Thanks, I will do that. I assume you mean the self tests in
tools/perf/tests and not some non Perf tests?

> Thanks,
> 
> Will

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[Will Deacon]

On Thu, Sep 22, 2022 at 03:31:20PM +0100, James Clark wrote:
> 
> 
> On 22/09/2022 15:04, Will Deacon wrote:
> > On Thu, Sep 01, 2022 at 02:26:56PM +0100, James Clark wrote:
> >> I'm resubmitting this with a few of the changes suggested by Will on V2.
> >>
> >> I haven't made any changes regarding the open questions about the
> >> discoverability or saving the new reg and passing to output_sample()
> >> because I think it's best to be consistent with the implementations on
> >> other platforms first. I have explained in more detail on v2 [1].
> >>
> >> [1]: https://lore.kernel.org/lkml/5fcf1a6f-c8fb-c296-992e-18aae8874095@arm.com/
> > 
> > Fair enough, I can't argue against being consistent.
> > 
> > Given that this exposes subtle new user ABI, do we have any coverage in
> > the selftests? If not, please could you add something?
> > 
> 
> Thanks, I will do that. I assume you mean the self tests in
> tools/perf/tests and not some non Perf tests?

I hadn't thought much about it, so wherever is best. It would just be nice
to have something we can run to make sure that this continues to work as
intended.

Will

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[Will Deacon]

On Thu, 1 Sep 2022 14:26:56 +0100, James Clark wrote:
> I'm resubmitting this with a few of the changes suggested by Will on V2.
> 
> I haven't made any changes regarding the open questions about the
> discoverability or saving the new reg and passing to output_sample()
> because I think it's best to be consistent with the implementations on
> other platforms first. I have explained in more detail on v2 [1].
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/2] perf: arm64: Add SVE vector granule register to user regs
      https://git.kernel.org/will/c/cbb0c02caf4b
[2/2] arm64/sve: Add Perf extensions documentation
      https://git.kernel.org/will/c/1f2906d1e10a

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[James Clark]

On 22/09/2022 21:33, Will Deacon wrote:
> On Thu, 1 Sep 2022 14:26:56 +0100, James Clark wrote:
>> I'm resubmitting this with a few of the changes suggested by Will on V2.
>>
>> I haven't made any changes regarding the open questions about the
>> discoverability or saving the new reg and passing to output_sample()
>> because I think it's best to be consistent with the implementations on
>> other platforms first. I have explained in more detail on v2 [1].
>>
>> [...]
> 
> Applied to will (for-next/perf), thanks!
> 
> [1/2] perf: arm64: Add SVE vector granule register to user regs
>       https://git.kernel.org/will/c/cbb0c02caf4b
> [2/2] arm64/sve: Add Perf extensions documentation
>       https://git.kernel.org/will/c/1f2906d1e10a
> 
> Cheers,

Thanks Will. Sorry about the build, I will fix my config for next time.

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[Will Deacon]

On Fri, Sep 23, 2022 at 10:32:15AM +0100, James Clark wrote:
> 
> 
> On 22/09/2022 21:33, Will Deacon wrote:
> > On Thu, 1 Sep 2022 14:26:56 +0100, James Clark wrote:
> >> I'm resubmitting this with a few of the changes suggested by Will on V2.
> >>
> >> I haven't made any changes regarding the open questions about the
> >> discoverability or saving the new reg and passing to output_sample()
> >> because I think it's best to be consistent with the implementations on
> >> other platforms first. I have explained in more detail on v2 [1].
> >>
> >> [...]
> > 
> > Applied to will (for-next/perf), thanks!
> > 
> > [1/2] perf: arm64: Add SVE vector granule register to user regs
> >       https://git.kernel.org/will/c/cbb0c02caf4b
> > [2/2] arm64/sve: Add Perf extensions documentation
> >       https://git.kernel.org/will/c/1f2906d1e10a
> > 
> > Cheers,
> 
> Thanks Will. Sorry about the build, I will fix my config for next time.

No problem. For some reason, I was unable to repro the failure locally.
Maybe it's a GCC thing?

Will

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Re: [PATCH v3 0/2] perf: arm64: Kernel support for Dwarf unwinding through SVE functions

[James Clark]

On 23/09/2022 13:36, Will Deacon wrote:
> On Fri, Sep 23, 2022 at 10:32:15AM +0100, James Clark wrote:
>>
>>
>> On 22/09/2022 21:33, Will Deacon wrote:
>>> On Thu, 1 Sep 2022 14:26:56 +0100, James Clark wrote:
>>>> I'm resubmitting this with a few of the changes suggested by Will on V2.
>>>>
>>>> I haven't made any changes regarding the open questions about the
>>>> discoverability or saving the new reg and passing to output_sample()
>>>> because I think it's best to be consistent with the implementations on
>>>> other platforms first. I have explained in more detail on v2 [1].
>>>>
>>>> [...]
>>>
>>> Applied to will (for-next/perf), thanks!
>>>
>>> [1/2] perf: arm64: Add SVE vector granule register to user regs
>>>       https://git.kernel.org/will/c/cbb0c02caf4b
>>> [2/2] arm64/sve: Add Perf extensions documentation
>>>       https://git.kernel.org/will/c/1f2906d1e10a
>>>
>>> Cheers,
>>
>> Thanks Will. Sorry about the build, I will fix my config for next time.
> 
> No problem. For some reason, I was unable to repro the failure locally.
> Maybe it's a GCC thing?

For me I needed CONFIG_HEADERS_INSTALL and CONFIG_UAPI_HEADER_TEST to
reproduce it. I was already using gcc, so not sure if it's depends on
that or not.

> 
> Will

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