From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Rajendra Nayak <rnayak@codeaurora.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
David Brown <david.brown@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Sibi Sankar <sibis@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RESEND PATCHv4 1/1] coresight: Do not default to CPU0 for missing CPU phandle
Date: Thu, 27 Jun 2019 23:51:56 +0530 [thread overview]
Message-ID: <0e33a1f2-f535-91e3-635d-dc8852833a0b@codeaurora.org> (raw)
In-Reply-To: <CANLsYkyaeroow1dRaffy5pxSCH7ocb9=EMeZeSjgpjDWXu18vg@mail.gmail.com>
On 6/27/2019 10:54 PM, Mathieu Poirier wrote:
>
> I want to apply your code to my tree but it isn't easy for me to do
> so. Did you notice the checkpatch.pl warning about the DT bindings
> being in a separate patch? In this case it is not a new binding but
> following the process gives the DT maintainers the opportunity to at
> least look at your patch. Because the changes are trivial they may
> decide to ignore it but that choice it theirs to make.
>
Hmm, git log on coresight dt-bindings showed some examples like
this where bindings were updated in the same patch.
Anyways, I have separated out the patch now and resent v5.
Thanks,
Sai
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prev parent reply other threads:[~2019-06-27 18:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 4:44 [RESEND PATCHv4 0/1] coresight: Do not default to CPU0 for missing CPU phandle Sai Prakash Ranjan
2019-06-27 4:44 ` [RESEND PATCHv4 1/1] " Sai Prakash Ranjan
2019-06-27 17:24 ` Mathieu Poirier
2019-06-27 18:21 ` Sai Prakash Ranjan [this message]
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