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Subject: Re: [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock
To: Jon Hunter <jonathanh@nvidia.com>, Thierry Reding
 <thierry.reding@gmail.com>, Peter De Schrijver <pdeschrijver@nvidia.com>
References: <20181204092548.3038-1-josephl@nvidia.com>
 <20181204092548.3038-17-josephl@nvidia.com>
 <827e05c8-13b9-fb5e-7bca-1a34b81763b1@nvidia.com>
From: Joseph Lo <josephl@nvidia.com>
Message-ID: <0f424403-50b7-983b-069b-1a7b757bf26a@nvidia.com>
Date: Tue, 11 Dec 2018 16:52:05 +0800
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On 12/7/18 10:57 PM, Jon Hunter wrote:
> 
> On 04/12/2018 09:25, Joseph Lo wrote:
>> Enable DFLL clock for Jetson TX1 platform.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>>   .../boot/dts/nvidia/tegra210-p2371-2180.dts   | 20 +++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> index 37e3c46e753f..53f497c2b3ff 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> @@ -78,4 +78,24 @@
>>   			};
>>   		};
>>   	};
>> +
>> +	clock@70110000 {
>> +		status = "okay";
>> +		nvidia,pwm-to-pmic;
>> +		nvidia,init-uv = <1000000>;
>> +		nvidia,align-offset-uv = <708000>;
>> +		nvidia,align-step-uv = <19200>;
>> +		nvidia,sample-rate = <25000>;
>> +		nvidia,droop-ctrl = <0x00000f00>;
>> +		nvidia,force-mode = <1>;
>> +		nvidia,cf = <6>;
>> +		nvidia,ci = <0>;
>> +		nvidia,cg = <2>;
>> +		nvidia,idle-override;
>> +		nvidia,one-shot-calibrate;
> 
> I don't see any Documentation for or usage of the above two properties.

Oops. Good catch. Will remove that.

Thanks.

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