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Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lZ8vJ-00CkCR-Rw; Wed, 21 Apr 2021 09:13:32 +0000 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lZ8v3-0001ux-7m; Wed, 21 Apr 2021 11:13:13 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: cl@rock-chips.com Cc: robh+dt@kernel.org, jagan@amarulasolutions.com, wens@csie.org, uwe@kleine-koenig.org, mail@david-bauer.net, jbx6244@gmail.com, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, jensenhuang@friendlyarm.com, michael@amarulasolutions.com, cnsztl@gmail.com, devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, linux-i2c@vger.kernel.org, jay.xu@rock-chips.com, shawn.lin@rock-chips.com, david.wu@rock-chips.com, zhangqing@rock-chips.com, huangtao@rock-chips.com, cl@rock-chips.com, ezequiel@collabora.com, kever.yang@rock-chips.com Subject: Re: [PATCH v1 4/5] arm64: dts: rockchip: add core dtsi for RK3568 SoC Date: Wed, 21 Apr 2021 11:13:11 +0200 Message-ID: <11131098.F0gNSz5aLb@diego> In-Reply-To: <20210421065921.23917-5-cl@rock-chips.com> References: <20210421065921.23917-1-cl@rock-chips.com> <20210421065921.23917-5-cl@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210421_021330_089489_4669D6FD X-CRM114-Status: GOOD ( 32.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Liang, Am Mittwoch, 21. April 2021, 08:59:20 CEST schrieb cl@rock-chips.com: > From: Liang Chen > > RK3568 is a high-performance and low power quad-core application processor > designed for personal mobile internet device and AIoT equipments. > > This patch add basic core dtsi file for it. > > Signed-off-by: Liang Chen this is a first round of basic stuff :-) . First of all, I really like the move of moving the pretty standardized pinconfig entries to the rockchip-pinconf.dtsi . (1) But please move this into a separate patch to make that more visible and maybe even convert _some_ or all arm64 Rockchip socs to use that as well "arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs The pinconfig settings for Rockchip SoCs are pretty similar on all socs, so move them to a shared dtsi to be included, instead of redefining them for each soc" (2) I also like the external rk3568-pinctrl approach with the dtsi getting auto-generated. This will probably help us in keeping pinctrl settings synchronous between mainline and the vendor kernel. (3) From my basic understanding the rk3568 is basically a rk3566 + more peripherals, so ideally they would share the basic ones in a rk3566.dtsi which the rk3568.dtsi then could include and extend with its additional peripherals. With at least the pine64 boards being based on the rk3566, there probably will be quite a mainline use of it as well. Or is there something that would prevent this? More below: > --- > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 2789 +++++++++++++++++ > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 795 +++++ > .../boot/dts/rockchip/rockchip-pinconf.dtsi | 346 ++ > 3 files changed, 3930 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > new file mode 100644 > index 000000000000..92b315763dc0 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi > @@ -0,0 +1,2789 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +#include > +#include "rockchip-pinconf.dtsi" > + > +/* > + * This file is auto generated by pin2dts tool, please keep these code > + * by adding changes at end of this file. > + */ > +&pinctrl { > + acodec { > + /omit-if-no-ref/ > + acodec_pins: acodec-pins { > + rockchip,pins = > + /* acodec_adc_sync */ > + <1 RK_PB1 5 &pcfg_pull_none>, > + /* acodec_adcclk */ > + <1 RK_PA1 5 &pcfg_pull_none>, > + /* acodec_adcdata */ > + <1 RK_PA0 5 &pcfg_pull_none>, > + /* acodec_dac_datal */ > + <1 RK_PA7 5 &pcfg_pull_none>, > + /* acodec_dac_datar */ > + <1 RK_PB0 5 &pcfg_pull_none>, > + /* acodec_dacclk */ > + <1 RK_PA3 5 &pcfg_pull_none>, > + /* acodec_dacsync */ > + <1 RK_PA5 5 &pcfg_pull_none>; > + }; > + }; can you adapt your pin2dts tool to insert a blank line here please? > + audiopwm { > + /omit-if-no-ref/ > + audiopwm_lout: audiopwm-lout { > + rockchip,pins = > + /* audiopwm_lout */ > + <1 RK_PA0 4 &pcfg_pull_none>; > + }; same here and of course below. I.e. in a list of subnodes it would be really nice if you could add a blank line above every subnode - except the first of course ;-) So, + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { does not get a blank line before audiopwm-lout, but between audiopwn-lout and the next sub node. > + /omit-if-no-ref/ > + audiopwm_loutn: audiopwm-loutn { > + rockchip,pins = > + /* audiopwm_loutn */ > + <1 RK_PA1 6 &pcfg_pull_none>; > + }; [...] > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > new file mode 100644 > index 000000000000..ac8db2f54f2b > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -0,0 +1,795 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "rockchip,rk3568"; > + > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial2 = &uart2; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + clocks = <&scmi_clk 0>; what is <&scmi_clk 0>. I see the rk3568 clk-driver defining our standard ARMCLK, so I'd ask for an explanation (in the commit message maybe) what makes the scmi clk different and especially what firmware-dependencies arise. Also it would be very cool if Rockchip could upstream rk3568-support to mainline TF-A, so that people don't need binary blobs for this. > + operating-points-v2 = <&cpu0_opp_table>; > + #cooling-cells = <2>; > + }; blank lines between nodes in the same hierarchy level > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + }; > + > + cpu0_opp_table: cpu0-opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-408000000 { > + opp-hz = /bits/ 64 <408000000>; > + opp-microvolt = <825000 825000 1150000>; > + clock-latency-ns = <40000>; > + }; > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <825000 825000 1150000>; > + }; > + opp-816000000 { > + opp-hz = /bits/ 64 <816000000>; > + opp-microvolt = <825000 825000 1150000>; > + opp-suspend; > + }; > + opp-1104000000 { > + opp-hz = /bits/ 64 <1104000000>; > + opp-microvolt = <825000 825000 1150000>; > + }; > + opp-1416000000 { > + opp-hz = /bits/ 64 <1416000000>; > + opp-microvolt = <900000 900000 1150000>; > + }; > + opp-1608000000 { > + opp-hz = /bits/ 64 <1608000000>; > + opp-microvolt = <975000 975000 1150000>; > + }; > + opp-1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <1050000 1050000 1150000>; > + }; > + opp-1992000000 { > + opp-hz = /bits/ 64 <1992000000>; > + opp-microvolt = <1150000 1150000 1150000>; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + firmware { > + scmi: scmi { > + compatible = "arm,scmi-smc"; > + shmem = <&scmi_shmem>; > + arm,smc-id = <0x82000010>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + }; > + > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + arm,no-tick-in-suspend; > + }; > + > + xin24m: xin24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + xin32k: xin32k { > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "xin32k"; > + #clock-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&clk32k_out0>; > + }; > + > + scmi_shmem: scmi-shmem@10f000 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x0010f000 0x0 0x100>; are you sure this works in mainline? I.e. looking at Documentation/devicetree/bindings/arm/arm,scmi.txt it talks about arm,scmi-shmem being part of a defined sram area while the node above seems to be in main memory? > + }; > + > + gic: interrupt-controller@fd400000 { > + compatible = "arm,gic-v3"; reg + interrupts up here below compatible please (+rest alphabetically sorted) > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + > + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ > + <0x0 0xfd460000 0 0xc0000>; /* GICR */ > + interrupts = ; > + }; > diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi > new file mode 100644 > index 000000000000..0c292ef8a87a > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi > @@ -0,0 +1,346 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + */ > + > +&pinctrl { no blank line here please ;-) The other blank lines below are correct though And as said at the top, please move into a separate patch and maybe convert some other Rockchip arm64 socs to it as well ;-) . > + > + /omit-if-no-ref/ > + pcfg_pull_up: pcfg-pull-up { > + bias-pull-up; > + }; > + > + /omit-if-no-ref/ > + pcfg_pull_down: pcfg-pull-down { > + bias-pull-down; > + }; > + > + /omit-if-no-ref/ > + pcfg_pull_none: pcfg-pull-none { > + bias-disable; > + }; > + Thanks Heiko _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel