From: Marc Zyngier <maz@kernel.org>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Thanu Rangarajan <thanu.rangarajan@arm.com>,
Souvik Chakravarty <souvik.chakravarty@arm.com>,
Jason Cooper <jason@lakedaemon.net>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
bcm-kernel-feedback-list@broadcom.com,
Jim Quinlan <james.quinlan@broadcom.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC 2/2] irqchip/gic: Allow the use of SGI interrupts
Date: Wed, 23 Oct 2019 14:22:34 +0100 [thread overview]
Message-ID: <112a725164b7fe321f27357fd4cd772f@www.loen.fr> (raw)
In-Reply-To: <20191023000547.7831-3-f.fainelli@gmail.com>
Hi Florian,
Needless to say, I mostly have questions...
On 2019-10-23 01:05, Florian Fainelli wrote:
> SGI interrupts are a convenient way for trusted firmware to target a
> specific set of CPUs. Update the ARM GIC code to allow the
> translation
> and mapping of SGI interrupts.
>
> Since the kernel already uses SGIs for various inter-processor
> interrupt
> activities, we specifically make sure that we do not let users of the
> IRQ API to even try to map those.
>
> Internal IPIs remain dispatched through handle_IPI() while public
> SGIs
> get promoted to a normal interrupt flow management.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/irqchip/irq-gic.c | 41
> +++++++++++++++++++++++++++------------
> 1 file changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 30ab623343d3..dcfdbaacdd64 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -385,7 +385,10 @@ static void __exception_irq_entry
> gic_handle_irq(struct pt_regs *regs)
> * Pairs with the write barrier in gic_raise_softirq
> */
> smp_rmb();
> - handle_IPI(irqnr, regs);
> + if (irqnr < NR_IPI)
> + handle_IPI(irqnr, regs);
> + else
> + handle_domain_irq(gic->domain, irqnr, regs);
Double EOI, UNPREDICTABLE territory, your state machine is now dead.
> #endif
> continue;
> }
> @@ -1005,20 +1008,34 @@ static int gic_irq_domain_translate(struct
> irq_domain *d,
> if (fwspec->param_count < 3)
> return -EINVAL;
>
> - /* Get the interrupt number and add 16 to skip over SGIs */
> - *hwirq = fwspec->param[1] + 16;
> -
> - /*
> - * For SPIs, we need to add 16 more to get the GIC irq
> - * ID number
> - */
> - if (!fwspec->param[0])
> + *hwirq = fwspec->param[1];
> + switch (fwspec->param[0]) {
> + case 0:
> + /*
> + * For SPIs, we need to add 16 more to get the GIC irq
> + * ID number
> + */
> + *hwirq += 16;
> + /* fall through */
> + case 1:
> + /* Add 16 to skip over SGIs */
> *hwirq += 16;
> + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
>
> - *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
> + /* Make it clear that broken DTs are... broken */
> + WARN_ON(*type == IRQ_TYPE_NONE);
> + break;
> + case 2:
> + /* Refuse to map internal IPIs */
> + if (*hwirq < NR_IPI)
So depending on how the kernel uses SGIs, you can or cannot use these
SGIs.
That looks like a good way to corner ourselves into not being to change
much.
Also, do you expect this to work for both Group-0 and Group-1
interrupts
(since you imply that this works as a communication medium with the
secure
side)? Given that the kernel running in NS has no way to enable/disable
Group-0 interrupts, this looks terminally flawed. Or is that Group-1
only?
How do we describe which SGIs are guaranteed to be available to Linux?
> + return -EPERM;
> +
> + *type = IRQ_TYPE_NONE;
Or not. SGI are edge triggered, by definition.
> + break;
> + default:
> + break;
> + }
>
> - /* Make it clear that broken DTs are... broken */
> - WARN_ON(*type == IRQ_TYPE_NONE);
Really?
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2019-10-23 13:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 0:05 [PATCH RFC 0/2] irqchip/gic: Allow the use of SGI interrupts Florian Fainelli
2019-10-23 0:05 ` [PATCH RFC 1/2] dt-bindings: Define interrupt type for " Florian Fainelli
2019-10-23 0:05 ` [PATCH RFC 2/2] irqchip/gic: Allow the use of " Florian Fainelli
2019-10-23 13:22 ` Marc Zyngier [this message]
2019-10-23 17:02 ` Florian Fainelli
2019-10-24 8:27 ` Marc Zyngier
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