From: Quanyang Wang <quanyang.wang@windriver.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
Michal Simek <michal.simek@xilinx.com>,
Rajan Vaja <rajan.vaja@xilinx.com>
Subject: Re: [PATCH] clk: zynqmp: pll: Fix divider calculation to avoid out-of-range rate
Date: Thu, 29 Sep 2022 09:05:10 +0800 [thread overview]
Message-ID: <11481209-7c8f-7543-1e04-5723ffc2ccd4@windriver.com> (raw)
In-Reply-To: <20220928201656.30318-1-laurent.pinchart@ideasonboard.com>
Hi Laurent,
I have sent a patch as below to fix this issue which set rate failed and
it's in linux-next repo now.
https://lore.kernel.org/linux-arm-kernel/20220826142030.213805-1-quanyang.wang@windriver.com/T/
As for the frequency gap between the requested rate and the actual, it's
because of the commit:
commit 948fb0969eae8
Author: Maxime Ripard <maxime@cerno.tech>
Date: Fri Feb 25 15:35:26 2022 +0100
clk: Always clamp the rounded rate
And I haven't figured out how to fix it.
Thanks,
Quanyang
On 9/29/22 04:16, Laurent Pinchart wrote:
> When calculating the divider in zynqmp_pll_round_rate() and
> zynqmp_pll_set_rate(), the division rounding error may result in an
> output frequency that is slightly outside of the PLL output range if the
> requested range is close to the low or high limit. As a result, the
> limits check in clk_calc_new_rates() would fail, and clk_set_rate()
> would return an error, as seen in the zynqmp-dpsub driver:
>
> [ 13.672309] zynqmp-dpsub fd4a0000.display: failed to set pixel clock rate to 297000000 (-22)
>
> Fix this by adjusting the divider. The rate calculation then succeeds
> for zynqmp-dpsub:
>
> [ 13.554849] zynqmp-dpsub fd4a0000.display: requested pixel rate: 297000000 actual rate: 255555553
>
> The resulting PLL configuration, however, is not optimal, as the rate
> error is 14%. The hardware can do much better, but CCF doesn't attempt
> to find the best overall configuration for cascaded clocks. That's a
> candidate for a separate fix.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/clk/zynqmp/pll.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
> index 91a6b4cc910e..be6fa44a21e0 100644
> --- a/drivers/clk/zynqmp/pll.c
> +++ b/drivers/clk/zynqmp/pll.c
> @@ -120,6 +120,10 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> }
>
> fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
> + if (*prate * fbdiv < PS_PLL_VCO_MIN)
> + fbdiv++;
> + if (*prate * fbdiv > PS_PLL_VCO_MAX)
> + fbdiv--;
> fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
> return *prate * fbdiv;
> }
> @@ -208,6 +212,10 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> }
>
> fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
> + if (parent_rate * fbdiv < PS_PLL_VCO_MIN)
> + fbdiv++;
> + else if (parent_rate * fbdiv > PS_PLL_VCO_MAX)
> + fbdiv--;
> fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
> ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
> if (ret)
>
> base-commit: 1c23f9e627a7b412978b4e852793c5e3c3efc555
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next prev parent reply other threads:[~2022-09-29 1:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 20:16 [PATCH] clk: zynqmp: pll: Fix divider calculation to avoid out-of-range rate Laurent Pinchart
2022-09-29 1:05 ` Quanyang Wang [this message]
2022-10-01 0:05 ` Stephen Boyd
2022-10-01 10:40 ` Maxime Ripard
2022-10-02 2:17 ` Quanyang Wang
2022-10-03 0:06 ` Laurent Pinchart
2022-10-10 8:49 ` Maxime Ripard
2022-10-10 12:12 ` Quanyang Wang
2022-10-10 12:49 ` Maxime Ripard
2022-10-11 3:11 ` Quanyang Wang
2022-10-11 12:27 ` Maxime Ripard
2022-10-02 23:45 ` Laurent Pinchart
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