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From: (Uwe Kleine-König)
Subject: [PATCH] ARM: imx: assert SCC gate stays enabled
Date: Mon,  2 Jul 2012 11:30:34 +0200
Message-ID: <> (raw)

The SCC clock is needed in internal boot mode and so must keep enabled.
This same issue was fixed for the pre-common-clk code in commit

	3d6e614 (mx35: Fix boot ROM hang in internal boot mode)

Cc: John Ogness <>
Cc: Hans J. Koch <>
Signed-off-by: Uwe Kleine-K?nig <>
 arch/arm/mach-imx/clk-imx35.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 920a8cc..c6422fb 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -201,7 +201,6 @@ int __init mx35_clocks_init()
 			pr_err("i.MX35 clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
 	clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
 	clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
 	clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
@@ -264,6 +263,14 @@ int __init mx35_clocks_init()
+	/*
+	 * SCC is needed to boot via mmc after a watchdog reset. The clock code
+	 * before conversion to common clk also enabled UART1 (which isn't
+	 * handled here and not needed for mmc) and IIM (which is enabled
+	 * unconditionally above).
+	 */
+	clk_prepare_enable(clk[scc_gate]);
 	imx_print_silicon_rev("i.MX35", mx35_revision());

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Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-02  9:30 Uwe Kleine-König [this message]
2012-07-04  7:02 ` Sascha Hauer

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