From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 03/21] arm64: GICv3 device tree binding documentation
Date: Mon, 30 Jun 2014 16:01:32 +0100 [thread overview]
Message-ID: <1404140510-5382-4-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1404140510-5382-1-git-send-email-marc.zyngier@arm.com>
Add the necessary documentation to support GICv3.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
Documentation/devicetree/bindings/arm/gic-v3.txt | 79 ++++++++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/gic-v3.txt
diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt
new file mode 100644
index 0000000..33cd05e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic-v3.txt
@@ -0,0 +1,79 @@
+* ARM Generic Interrupt Controller, version 3
+
+AArch64 SMP cores are often associated with a GICv3, providing Private
+Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
+Software Generated Interrupts (SGI), and Locality-specific Peripheral
+Interrupts (LPI).
+
+Main node required properties:
+
+- compatible : should at least contain "arm,gic-v3".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. Must be a single cell with a value of at least 3.
+
+ The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+ interrupts. Other values are reserved for future use.
+
+ The 2nd cell contains the interrupt number for the interrupt type.
+ SPI interrupts are in the range [0-987]. PPI interrupts are in the
+ range [0-15].
+
+ The 3rd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = edge triggered
+ 4 = level triggered
+
+ Cells 4 and beyond are reserved for future use. When the 1st cell
+ has a value of 0 or 1, cells 4 and beyond act as padding, and may be
+ ignored. It is recommended that padding cells have a value of 0.
+
+- reg : Specifies base physical address(s) and size of the GIC
+ registers, in the following order:
+ - GIC Distributor interface (GICD)
+ - GIC Redistributors (GICR), one range per redistributor region
+ - GIC CPU interface (GICC)
+ - GIC Hypervisor interface (GICH)
+ - GIC Virtual CPU interface (GICV)
+
+ GICC, GICH and GICV are optional.
+
+- interrupts : Interrupt source of the VGIC maintenance interrupt.
+
+Optional
+
+- redistributor-stride : If using padding pages, specifies the stride
+ of consecutive redistributors. Must be a multiple of 64kB.
+
+- #redistributor-regions: The number of independent contiguous regions
+ occupied by the redistributors. Required if more than one such
+ region is present.
+
+Examples:
+
+ gic: interrupt-controller at 2cf00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x2f000000 0 0x10000>, // GICD
+ <0x0 0x2f100000 0 0x200000>, // GICR
+ <0x0 0x2c000000 0 0x2000>, // GICC
+ <0x0 0x2c010000 0 0x2000>, // GICH
+ <0x0 0x2c020000 0 0x2000>; // GICV
+ interrupts = <1 9 4>;
+ };
+
+ gic: interrupt-controller at 2c010000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x40000>; // 256kB stride
+ #redistributor-regions = <2>;
+ reg = <0x0 0x2c010000 0 0x10000>, // GICD
+ <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
+ <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
+ <0x0 0x2c040000 0 0x2000>, // GICC
+ <0x0 0x2c060000 0 0x2000>, // GICH
+ <0x0 0x2c080000 0 0x2000>; // GICV
+ interrupts = <1 9 4>;
+ };
--
2.0.0
next prev parent reply other threads:[~2014-06-30 15:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-30 15:01 [PATCH v6 00/21] arm64: GICv3 support Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 01/21] irqchip: ARM: GIC: Move some bits of GICv2 to a library-type file Marc Zyngier
2014-07-08 22:31 ` Jason Cooper
2014-07-11 16:15 ` Christoffer Dall
2014-07-11 20:47 ` Paolo Bonzini
2014-07-11 21:41 ` Christoffer Dall
2014-06-30 15:01 ` [PATCH v6 02/21] irqchip: arm64: Initial support for GICv3 Marc Zyngier
2014-06-30 17:58 ` Mark Rutland
2014-06-30 15:01 ` Marc Zyngier [this message]
2014-06-30 16:09 ` [PATCH v6 03/21] arm64: GICv3 device tree binding documentation Mark Rutland
2014-06-30 15:01 ` [PATCH v6 04/21] arm64: boot protocol documentation update for GICv3 Marc Zyngier
2014-06-30 15:56 ` Mark Rutland
2014-06-30 15:01 ` [PATCH v6 05/21] KVM: arm/arm64: vgic: move GICv2 registers to their own structure Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 06/21] KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 07/21] KVM: ARM: vgic: abstract access to the ELRSR bitmap Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 08/21] KVM: ARM: vgic: abstract EISR bitmap access Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 09/21] KVM: ARM: vgic: abstract MISR decoding Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 10/21] KVM: ARM: vgic: move underflow handling to vgic_ops Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 11/21] KVM: ARM: vgic: abstract VMCR access Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 12/21] KVM: ARM: vgic: introduce vgic_enable Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 13/21] KVM: ARM: introduce vgic_params structure Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 14/21] KVM: ARM: vgic: split GICv2 backend from the main vgic code Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 15/21] KVM: ARM: vgic: revisit implementation of irqchip_in_kernel Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 16/21] arm64: KVM: remove __kvm_hyp_code_{start, end} from hyp.S Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 17/21] arm64: KVM: split GICv2 world switch from hyp code Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 18/21] arm64: KVM: move HCR_EL2.{IMO, FMO} manipulation into the vgic switch code Marc Zyngier
2014-06-30 15:01 ` [PATCH v6 19/21] KVM: ARM: vgic: add the GICv3 backend Marc Zyngier
2014-07-04 9:42 ` Christoffer Dall
2014-06-30 15:01 ` [PATCH v6 20/21] arm64: KVM: vgic: add GICv3 world switch Marc Zyngier
2014-07-01 18:24 ` Will Deacon
2014-06-30 15:01 ` [PATCH v6 21/21] arm64: KVM: vgic: enable GICv2 emulation on top on GICv3 hardware Marc Zyngier
2014-07-04 9:58 ` Christoffer Dall
2014-06-30 15:43 ` [PATCH v6 00/21] arm64: GICv3 support Jason Cooper
2014-06-30 15:50 ` Marc Zyngier
2014-07-03 17:45 ` Marc Zyngier
2014-07-08 21:44 ` Jason Cooper
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