From: zlim.lnx@gmail.com (Zi Shen Lim)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/14] arm64: introduce aarch64_insn_gen_logical_shifted_reg()
Date: Fri, 18 Jul 2014 11:28:19 -0700 [thread overview]
Message-ID: <1405708100-13604-14-git-send-email-zlim.lnx@gmail.com> (raw)
In-Reply-To: <1405708100-13604-1-git-send-email-zlim.lnx@gmail.com>
Introduce function to generate logical (shifted register)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
---
arch/arm64/include/asm/insn.h | 25 ++++++++++++++++++
arch/arm64/kernel/insn.c | 60 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 36e8465..56a9e63 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -206,6 +206,17 @@ enum aarch64_insn_data3_type {
AARCH64_INSN_DATA3_MSUB,
};
+enum aarch64_insn_logic_type {
+ AARCH64_INSN_LOGIC_AND,
+ AARCH64_INSN_LOGIC_BIC,
+ AARCH64_INSN_LOGIC_ORR,
+ AARCH64_INSN_LOGIC_ORN,
+ AARCH64_INSN_LOGIC_EOR,
+ AARCH64_INSN_LOGIC_EON,
+ AARCH64_INSN_LOGIC_AND_SETFLAGS,
+ AARCH64_INSN_LOGIC_BIC_SETFLAGS
+};
+
#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
{ return (code & (mask)) == (val); } \
@@ -243,6 +254,14 @@ __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
+__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
+__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
+__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
+__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
+__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
+__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
+__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
+__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000)
@@ -323,6 +342,12 @@ u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
enum aarch64_insn_register reg2,
enum aarch64_insn_variant variant,
enum aarch64_insn_data3_type type);
+u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
+ enum aarch64_insn_register src,
+ enum aarch64_insn_register reg,
+ int shift,
+ enum aarch64_insn_variant variant,
+ enum aarch64_insn_logic_type type);
bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index f73a4bf..0668ee5 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -874,3 +874,63 @@ u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
reg2);
}
+
+u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
+ enum aarch64_insn_register src,
+ enum aarch64_insn_register reg,
+ int shift,
+ enum aarch64_insn_variant variant,
+ enum aarch64_insn_logic_type type)
+{
+ u32 insn;
+
+ switch (type) {
+ case AARCH64_INSN_LOGIC_AND:
+ insn = aarch64_insn_get_and_value();
+ break;
+ case AARCH64_INSN_LOGIC_BIC:
+ insn = aarch64_insn_get_bic_value();
+ break;
+ case AARCH64_INSN_LOGIC_ORR:
+ insn = aarch64_insn_get_orr_value();
+ break;
+ case AARCH64_INSN_LOGIC_ORN:
+ insn = aarch64_insn_get_orn_value();
+ break;
+ case AARCH64_INSN_LOGIC_EOR:
+ insn = aarch64_insn_get_eor_value();
+ break;
+ case AARCH64_INSN_LOGIC_EON:
+ insn = aarch64_insn_get_eon_value();
+ break;
+ case AARCH64_INSN_LOGIC_AND_SETFLAGS:
+ insn = aarch64_insn_get_ands_value();
+ break;
+ case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
+ insn = aarch64_insn_get_bics_value();
+ break;
+ default:
+ BUG_ON(1);
+ }
+
+ switch (variant) {
+ case AARCH64_INSN_VARIANT_32BIT:
+ BUG_ON(shift & ~(SZ_32 - 1));
+ break;
+ case AARCH64_INSN_VARIANT_64BIT:
+ insn |= AARCH64_INSN_SF_BIT;
+ BUG_ON(shift & ~(SZ_64 - 1));
+ break;
+ default:
+ BUG_ON(1);
+ }
+
+
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
+
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
+
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
+
+ return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
+}
--
1.9.1
next prev parent reply other threads:[~2014-07-18 18:28 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-18 18:28 [PATCH 00/14] arm64: eBPF JIT compiler Zi Shen Lim
2014-07-18 18:28 ` [PATCH 01/14] arm64: introduce aarch64_insn_gen_comp_branch_imm() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 02/14] arm64: introduce aarch64_insn_gen_branch_reg() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 03/14] arm64: introduce aarch64_insn_gen_cond_branch_imm() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 04/14] arm64: introduce aarch64_insn_gen_load_store_reg() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 05/14] arm64: introduce aarch64_insn_gen_load_store_pair() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 06/14] arm64: introduce aarch64_insn_gen_add_sub_imm() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 07/14] arm64: introduce aarch64_insn_gen_bitfield() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 08/14] arm64: introduce aarch64_insn_gen_movewide() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 09/14] arm64: introduce aarch64_insn_gen_add_sub_shifted_reg() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 10/14] arm64: introduce aarch64_insn_gen_data1() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 11/14] arm64: introduce aarch64_insn_gen_data2() Zi Shen Lim
2014-07-18 18:28 ` [PATCH 12/14] arm64: introduce aarch64_insn_gen_data3() Zi Shen Lim
2014-07-18 18:28 ` Zi Shen Lim [this message]
2014-07-18 18:28 ` [PATCH 14/14] arm64: eBPF JIT compiler Zi Shen Lim
2014-07-21 9:16 ` [PATCH 00/14] " Will Deacon
2014-07-21 15:49 ` Alexei Starovoitov
2014-07-23 5:24 ` Z Lim
2014-07-23 21:57 ` David Miller
2014-07-23 10:32 ` Catalin Marinas
2014-07-24 4:55 ` Z Lim
2014-07-24 11:32 ` Will Deacon
2014-08-26 9:58 ` Will Deacon
2014-08-27 2:02 ` Z Lim
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1405708100-13604-14-git-send-email-zlim.lnx@gmail.com \
--to=zlim.lnx@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).