From mboxrd@z Thu Jan 1 00:00:00 1970 From: ttynkkynen@nvidia.com (Tuomas Tynkkynen) Date: Mon, 21 Jul 2014 18:38:56 +0300 Subject: [PATCH v2 10/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock In-Reply-To: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> References: <1405957142-19416-1-git-send-email-ttynkkynen@nvidia.com> Message-ID: <1405957142-19416-11-git-send-email-ttynkkynen@nvidia.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen --- v2 changes: - none drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201..f1f4410 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", - "unused", "pll_x" }; + "unused", "pll_x", "unused", "unused", + "unused", "unused", "unused", "unused", + "dfllCPU_out" }; static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", -- 1.8.1.5