From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 08/16] ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
Date: Wed, 23 Jul 2014 15:00:45 +0200 [thread overview]
Message-ID: <1406120453-29291-9-git-send-email-thomas.petazzoni@free-electrons.com> (raw)
In-Reply-To: <1406120453-29291-1-git-send-email-thomas.petazzoni@free-electrons.com>
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B
core), the snoop disabling feature does not exist as the hardware
coherency is handled in a different way. Therefore, in preparation to
the introduction of the cpuidle support for those SoCs, this commit
modifies the mvebu_v7_psmu_idle_prepare() function to take several
flags, which allow to decide whether snooping should be disabled, and
whether we should use the deep idle mode or not.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
arch/arm/mach-mvebu/pmsu.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index ab525b7..15e67bf 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -191,8 +191,14 @@ static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}
+enum pmsu_idle_prepare_flags {
+ PMSU_PREPARE_NORMAL = 0,
+ PMSU_PREPARE_DEEP_IDLE = BIT(0),
+ PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
+};
+
/* No locking is needed because we only access per-CPU registers */
-static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
+static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
{
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
u32 reg;
@@ -216,26 +222,32 @@ static int mvebu_v7_pmsu_idle_prepare(bool deepidle)
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
/* ask HW to power down the L2 Cache if needed */
- if (deepidle)
+ if (flags & PMSU_PREPARE_DEEP_IDLE)
reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
/* request power down */
reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
- /* Disable snoop disable by HW - SW is taking care of it */
- reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
- reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
- writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
+ /* Disable snoop disable by HW - SW is taking care of it */
+ reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
+ writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+ }
return 0;
}
int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
+ unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
int ret;
- ret = mvebu_v7_pmsu_idle_prepare(deepidle);
+ if (deepidle)
+ flags |= PMSU_PREPARE_DEEP_IDLE;
+
+ ret = mvebu_v7_pmsu_idle_prepare(flags);
if (ret)
return ret;
--
2.0.0
next prev parent reply other threads:[~2014-07-23 13:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-23 13:00 [PATCHv3 00/16] cpuidle for Marvell Armada 370 and 38x Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 01/16] ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 02/16] ARM: mvebu: sort the #include of pmsu.c in alphabetic order Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 03/16] ARM: mvebu: add a common function for the boot address work around Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 04/16] ARM: mvebu: use the common function for Armada 375 SMP workaround Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 05/16] ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 06/16] ARM: mvebu: make the cpuidle initialization more generic Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 07/16] ARM: mvebu: use a local variable to store the resume address Thomas Petazzoni
2014-07-23 13:00 ` Thomas Petazzoni [this message]
2014-07-23 13:00 ` [PATCHv3 09/16] ARM: mvebu: export the SCU address Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 10/16] ARM: mvebu: add CA9 MPcore SoC Controller node Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 11/16] cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 Thomas Petazzoni
2014-07-24 9:15 ` Daniel Lezcano
2014-07-24 12:00 ` Jason Cooper
2014-07-23 13:00 ` [PATCHv3 12/16] cpuidle: mvebu: add Armada 370 support Thomas Petazzoni
2014-07-24 9:17 ` Daniel Lezcano
2014-07-23 13:00 ` [PATCHv3 13/16] cpuidle: mvebu: add Armada 38x support Thomas Petazzoni
2014-07-24 9:17 ` Daniel Lezcano
2014-07-23 13:00 ` [PATCHv3 14/16] ARM: mvebu: add cpuidle support for Armada 370 Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 15/16] ARM: mvebu: add cpuidle support for Armada 38x Thomas Petazzoni
2014-07-23 13:00 ` [PATCHv3 16/16] ARM: mvebu: defconfig: enable cpuidle support in mvebu_v7_defconfig Thomas Petazzoni
2014-07-24 12:03 ` [PATCHv3 00/16] cpuidle for Marvell Armada 370 and 38x Jason Cooper
2014-07-24 12:10 ` Thomas Petazzoni
2014-07-25 0:05 ` Jason Cooper
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