From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] arm64: alternative: Introduce feature for GICv3 CPU interface
Date: Thu, 19 Mar 2015 13:59:35 +0000 [thread overview]
Message-ID: <1426773576-14062-5-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1426773576-14062-1-git-send-email-marc.zyngier@arm.com>
Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF)
to indicate that we have a system register GIC CPU interface
This will help KVM switching to alternative instruction patching.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/cpufeature.h | 8 +++++++-
arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 6ae35d1..d9e57b5 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -23,8 +23,9 @@
#define ARM64_WORKAROUND_CLEAN_CACHE 0
#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
+#define ARM64_HAS_SYSREG_GIC_CPUIF 2
-#define ARM64_NCAPS 2
+#define ARM64_NCAPS 3
#ifndef __ASSEMBLY__
@@ -37,6 +38,11 @@ struct arm64_cpu_capabilities {
u32 midr_model;
u32 midr_range_min, midr_range_max;
};
+
+ struct { /* Feature register checking */
+ u64 register_mask;
+ u64 register_value;
+ };
};
};
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3d9967e..b0bea2b3 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -22,7 +22,23 @@
#include <asm/cpu.h>
#include <asm/cpufeature.h>
+static bool
+has_id_aa64pfr0_feature(const struct arm64_cpu_capabilities *entry)
+{
+ u64 val;
+
+ val = read_cpuid(id_aa64pfr0_el1);
+ return (val & entry->register_mask) == entry->register_value;
+}
+
static const struct arm64_cpu_capabilities arm64_features[] = {
+ {
+ .desc = "system register GIC CPU interface",
+ .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
+ .matches = has_id_aa64pfr0_feature,
+ .register_mask = (0xf << 24),
+ .register_value = (1 << 24),
+ },
{},
};
--
2.1.4
next prev parent reply other threads:[~2015-03-19 13:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-19 13:59 [PATCH 0/5] arm64: Patching branches for fun and profit Marc Zyngier
2015-03-19 13:59 ` [PATCH 1/5] arm64: insn: Add aarch64_insn_decode_immediate Marc Zyngier
2015-03-19 13:59 ` [PATCH 2/5] arm64: alternative: Allow immediate branch as alternative instruction Marc Zyngier
2015-03-26 22:03 ` Will Deacon
2015-03-26 22:19 ` Marc Zyngier
2015-03-26 22:31 ` Will Deacon
2015-03-27 10:42 ` Jon Medhurst (Tixy)
2015-03-27 11:08 ` Marc Zyngier
2015-03-19 13:59 ` [PATCH 3/5] arm64: Extract feature parsing code from cpu_errata.c Marc Zyngier
2015-03-19 13:59 ` Marc Zyngier [this message]
2015-03-19 13:59 ` [PATCH 5/5] arm64: KVM: Switch vgic save/restore to alternative_insn Marc Zyngier
2015-03-26 22:04 ` [PATCH 0/5] arm64: Patching branches for fun and profit Will Deacon
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