From: erin.lo@mediatek.com (Erin Lo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 10/10] arm: dts: mt2701: Use real clock for UARTs
Date: Wed, 22 Jun 2016 15:40:29 +0800 [thread overview]
Message-ID: <1466581229-2342-11-git-send-email-erin.lo@mediatek.com> (raw)
In-Reply-To: <1466581229-2342-1-git-send-email-erin.lo@mediatek.com>
We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index c9a8dbf..7eab6f4 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -73,12 +73,6 @@
#clock-cells = <0>;
};
- uart_clk: dummy26m {
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- #clock-cells = <0>;
- };
-
clk26m: oscillator at 0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -186,7 +180,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -195,7 +190,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -204,7 +200,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -213,7 +210,8 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
status = "disabled";
};
};
--
1.9.1
prev parent reply other threads:[~2016-06-22 7:40 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-22 7:40 [PATCH v9 00/10] Add clock support for Mediatek MT2701 Erin Lo
2016-06-22 7:40 ` [PATCH v9 01/10] clk: fix initial state of critical clock's parents Erin Lo
2016-07-02 1:21 ` Stephen Boyd
2016-07-04 3:51 ` James Liao
2016-07-08 23:32 ` Michael Turquette
2016-07-09 0:46 ` Stephen Boyd
2016-07-11 8:24 ` James Liao
2016-08-03 5:46 ` James Liao
2016-08-09 5:39 ` James Liao
2016-08-10 21:09 ` Stephen Boyd
2016-08-12 8:17 ` James Liao
2016-08-13 0:39 ` Stephen Boyd
2016-08-15 2:47 ` James Liao
2016-06-22 7:40 ` [PATCH v9 02/10] clk: mediatek: remove __init from clk registration functions Erin Lo
2016-06-22 7:40 ` [PATCH v9 03/10] clk: mediatek: Refine the makefile to support multiple clock drivers Erin Lo
2016-08-13 0:41 ` Stephen Boyd
2016-06-22 7:40 ` [PATCH v9 04/10] dt-bindings: ARM: Mediatek: Document bindings for MT2701 Erin Lo
2016-06-22 7:40 ` [PATCH v9 05/10] clk: mediatek: Add dt-bindings for MT2701 clocks Erin Lo
2016-06-22 7:40 ` [PATCH v9 06/10] clk: mediatek: Add MT2701 clock support Erin Lo
2016-08-13 0:44 ` Stephen Boyd
2016-08-15 3:00 ` James Liao
2016-08-15 18:16 ` Stephen Boyd
2016-06-22 7:40 ` [PATCH v9 07/10] reset: mediatek: Add MT2701 reset controller dt-binding file Erin Lo
2016-06-22 7:40 ` [PATCH v9 08/10] reset: mediatek: Add MT2701 reset driver Erin Lo
2016-06-22 7:40 ` [PATCH v9 09/10] arm: dts: mt2701: Add clock controller device nodes Erin Lo
2016-06-22 7:40 ` Erin Lo [this message]
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