From: jszhang@marvell.com (Jisheng Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
Date: Wed, 6 Jul 2016 18:59:40 +0800 [thread overview]
Message-ID: <1467802782-3024-1-git-send-email-jszhang@marvell.com> (raw)
patch1 is a trivial clean up: move the parameters for wait for link
into the core pcie-designware.c
Since link may be UP but still in link training, if so, we can't think
the link is up and operating correctly. So patch2 teaches
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
Jisheng Zhang (2):
PCI: designware: mv parameters for wait for link into
pcie-designware.c
PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
drivers/pci/host/pcie-designware.c | 11 +++++++++--
drivers/pci/host/pcie-designware.h | 5 -----
2 files changed, 9 insertions(+), 7 deletions(-)
--
2.8.1
next reply other threads:[~2016-07-06 10:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-06 10:59 Jisheng Zhang [this message]
2016-07-06 10:59 ` [PATCH 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
2016-07-06 10:59 ` [PATCH 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-07-15 15:10 ` Joao Pinto
2016-07-18 2:38 ` Jisheng Zhang
2016-07-21 10:11 ` Joao Pinto
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