* [PATCH 00/12] aspeed: Add pinctrl and gpio drivers
@ 2016-07-20 5:58 Andrew Jeffery
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
` (11 more replies)
0 siblings, 12 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This series is an evolution of the AST2400 pinctrl RFC posted a few months
back:
http://www.spinics.net/lists/linux-gpio/msg14414.html
The approach is similar to the RFC but a number of details have changed, often
to support the weirder mux configuration cases. Unlike the RFC this series
separates the common code for 4th and 5th generation SoC support and integrates
the code into the kernel at large. The GPIO driver is included so it can
integrate with pinctrl from the outset; the code already existed but had not
yet been sent upstream.
The series has been tested on both the AST2400 (g4) and AST2500 (g5) SoCs on
OpenPOWER Palmetto and Aspeed AST2500 EVB machines respectively, and similarly
in qemu where models were available.
As mentioned in the RFC cover letter this is my first significant contribution
to the kernel so I fully expect I've made some oversights; apologies in advance
if I've missed anything required or obvious!
Cheers,
Andrew
Andrew Jeffery (11):
pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
pinctrl: Add core pinctrl support for Aspeed SoCs
pinctrl: Add pinctrl-aspeed-g4 driver
pinctrl: Add pinctrl-aspeed-g5 driver
gpio: dt-bindings: Add documentation for Aspeed GPIO controllers
syscon: dt-bindings: Add documentation for Aspeed system control units
aspeed-g4: Add syscon and pin controller nodes
palmetto: Request relevant mux functions in devicetree
aspeed-g4: Add gpio controller to devicetree
aspeed-g5: Add syscon and pin controller nodes
aspeed-g5: Add gpio controller to devicetree
Joel Stanley (1):
gpio: Add Aspeed driver
.../devicetree/bindings/gpio/gpio-aspeed.txt | 42 +
.../devicetree/bindings/mfd/aspeed-scu.txt | 16 +
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 +
MAINTAINERS | 2 +
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 28 +
arch/arm/boot/dts/aspeed-g4.dtsi | 293 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 143 +++
arch/arm/mach-aspeed/Kconfig | 7 +
drivers/gpio/Kconfig | 8 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-aspeed.c | 456 ++++++++
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Kconfig | 24 +
drivers/pinctrl/aspeed/Makefile | 5 +
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1091 ++++++++++++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 561 ++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 373 +++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 562 ++++++++++
19 files changed, 3658 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
create mode 100644 drivers/gpio/gpio-aspeed.c
create mode 100644 drivers/pinctrl/aspeed/Kconfig
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.c
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.h
--
2.7.4
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 19:05 ` Rob Herring
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
` (10 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Outline expectations on the pin controller's relationship with the
System Control Unit (SCU) IP through syscon, and document the compatible
strings for 4th and 5th generation Aspeed SoC pin controllers.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5aac6a0a2e89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,45 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible: should be one of the following:
+ "aspeed,g4-pinctrl";
+ "aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode format:
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function.
+
+Examples:
+
+syscon: scu at 1e6e2000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl at 1e6e2000 {
+ compatible = "aspeed,g4-pinctrl";
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+ };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1209323b7e43..b5f2d3576d3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1003,6 +1003,7 @@ S: Maintained
F: arch/arm/mach-aspeed/
F: arch/arm/boot/dts/aspeed-*
F: drivers/*/*aspeed*
+F: Documentation/devicetree/bindings/*/*aspeed*
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@atmel.com>
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-22 6:29 ` Joel Stanley
2016-08-11 8:41 ` Linus Walleij
2016-07-20 5:58 ` [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
` (9 subsequent siblings)
11 siblings, 2 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
The Aspeed SoCs provide typically more than 200 pins for GPIO and other
functions. The signal enabled on a pin is determined on a priority
basis, where a given pin can provide a number of different signal types.
In addition to the priority levels, the Aspeed pin controllers describe
the signal active on a pin by compound logical expressions involving
multiple operators, registers and bits. Some difficulty arises as a
pin's function bit masks for each priority level are frequently not the
same (i.e. we cannot just flip a bit to change from a high to low
priority signal), or even in the same register(s). Some configuration
bits affect multiple pins, while in other cases the signals for a bus
must each be enabled individually.
Together, these features give rise to some complexity in the
implementation. A more complete description of the complexities is
provided in the associated header file in an attempt to justify the
approach.
Note that the patch doesn't implement pinctrl/pinmux/pinconf for any
particular SoC, just adds the framework for defining mux configurations
for any available functions.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
MAINTAINERS | 1 +
arch/arm/mach-aspeed/Kconfig | 1 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Kconfig | 8 +
drivers/pinctrl/aspeed/Makefile | 3 +
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 373 +++++++++++++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 562 ++++++++++++++++++++++++++++++++
8 files changed, 950 insertions(+)
create mode 100644 drivers/pinctrl/aspeed/Kconfig
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.c
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b5f2d3576d3a..f6987de35435 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1004,6 +1004,7 @@ F: arch/arm/mach-aspeed/
F: arch/arm/boot/dts/aspeed-*
F: drivers/*/*aspeed*
F: Documentation/devicetree/bindings/*/*aspeed*
+F: drivers/pinctrl/aspeed/
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@atmel.com>
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index 5225fbcb250d..632899c58098 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -5,6 +5,7 @@ menuconfig ARCH_ASPEED
select WATCHDOG
select ASPEED_WATCHDOG
select MOXART_TIMER
+ select PINCTRL
help
Say Y here if you want to run your kernel on an ASpeed BMC SoC.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index fb8200b8e8ec..299e4531f677 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -232,6 +232,7 @@ config PINCTRL_ZYNQ
help
This selects the pinctrl driver for Xilinx Zynq.
+source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/freescale/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 42a5c1dddfef..161eb5d1d878 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
+obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_BCM) += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
new file mode 100644
index 000000000000..34d9050f2761
--- /dev/null
+++ b/drivers/pinctrl/aspeed/Kconfig
@@ -0,0 +1,8 @@
+config PINCTRL_ASPEED
+ bool
+ depends on (ARCH_ASPEED || COMPILE_TEST) && OF
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select MFD_SYSCON
+ select REGMAP_MMIO
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
new file mode 100644
index 000000000000..6bc001c001ee
--- /dev/null
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -0,0 +1,3 @@
+# Aspeed pinctrl support
+
+obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
new file mode 100644
index 000000000000..07d09e04a6ed
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include "../core.h"
+#include "pinctrl-aspeed.h"
+
+int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ return pdata->ngroups;
+}
+
+const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ return pdata->groups[group].name;
+}
+
+int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group, const unsigned int **pins,
+ unsigned int *npins)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &pdata->groups[group].pins[0];
+ *npins = pdata->groups[group].npins;
+
+ return 0;
+}
+
+void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int offset)
+{
+ seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+
+int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ return pdata->nfunctions;
+}
+
+const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ return pdata->functions[function].name;
+}
+
+int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
+ unsigned int function, const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pdata->functions[function].groups;
+ *num_groups = pdata->functions[function].ngroups;
+
+ return 0;
+}
+
+static inline void aspeed_sig_desc_print_val(
+ const struct aspeed_sig_desc *desc, bool enable, u32 rv)
+{
+#if defined(CONFIG_DEBUG_PINCTRL)
+ pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
+ desc->mask, enable ? desc->enable : desc->disable,
+ (rv & desc->mask) >> __ffs(desc->mask), rv);
+#endif
+}
+
+static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
+ bool enabled, struct regmap *map)
+{
+ unsigned int raw;
+ u32 want;
+
+ if (regmap_read(map, desc->reg, &raw) < 0)
+ return false;
+
+ aspeed_sig_desc_print_val(desc, enabled, raw);
+ want = enabled ? desc->enable : desc->disable;
+
+ return ((raw & desc->mask) >> __ffs(desc->mask)) == want;
+}
+
+static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
+ bool enabled, struct regmap *map)
+{
+ int i;
+
+ for (i = 0; i < expr->ndescs; i++) {
+ const struct aspeed_sig_desc *desc = &expr->descs[i];
+
+ if (!aspeed_sig_desc_eval(desc, enabled, map))
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * Configure a signal state by applying descriptor state for all descriptors in
+ * a signal expression.
+ *
+ * @expr: The expression associated with the function whose signal is to be
+ * configured
+ * @enable: true to enable an function's signal through a pin's signal
+ * expression, false to disable the function's signal
+ * @map: The SCU's regmap instance for pinmux register access.
+ *
+ * @return true if the expression is configured as requested, false otherwise
+ */
+static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
+ bool enable, struct regmap *map)
+{
+ int i;
+ bool ret;
+
+ ret = aspeed_sig_expr_eval(expr, enable, map);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < expr->ndescs; i++) {
+ const struct aspeed_sig_desc *desc = &expr->descs[i];
+ u32 pattern = enable ? desc->enable : desc->disable;
+ unsigned int val;
+
+ /*
+ * Strap registers are configured in hardware or by early-boot
+ * firmware. Treat them as read-only despite that we can write
+ * them. This may mean that certain functions cannot be
+ * deconfigured and is the reason we re-evaluate after writing
+ * all descriptor bits.
+ */
+ if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2)
+ continue;
+
+ if (regmap_read(map, desc->reg, &val) < 0)
+ return false;
+
+ val &= ~desc->mask;
+ val |= pattern << __ffs(desc->mask);
+
+ if (regmap_write(map, desc->reg, val) < 0)
+ return false;
+ }
+
+ return aspeed_sig_expr_eval(expr, enable, map);
+}
+
+static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
+ struct regmap *map)
+{
+ return aspeed_sig_expr_set(expr, true, map);
+}
+
+static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
+ struct regmap *map)
+{
+ return aspeed_sig_expr_set(expr, false, map);
+}
+
+/**
+ * Disable a signal on a pin by disabling all provided signal expressions.
+ *
+ * @exprs: The list of signal expressions (from a priority level on a pin)
+ * @map: The SCU's regmap instance for pinmux register access.
+ *
+ * @return true if all expressions in the list are successfully disabled, false
+ * otherwise
+ */
+static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
+ struct regmap *map)
+{
+ bool disabled = true;
+
+ if (!exprs)
+ return true;
+
+ while (*exprs) {
+ bool ret;
+
+ ret = aspeed_sig_expr_disable(*exprs, map);
+ disabled = disabled && ret;
+
+ exprs++;
+ }
+
+ return disabled;
+}
+
+/**
+ * Search for the signal expression needed to enable the pin's signal for the
+ * requested function.
+ *
+ * @exprs: List of signal expressions (haystack)
+ * @name: The name of the requested function (needle)
+ *
+ * @return A pointer to the signal expression whose function tag matches the
+ * provided name, otherwise NULL.
+ *
+ */
+static const struct aspeed_sig_expr *aspeed_find_expr_by_name(
+ const struct aspeed_sig_expr **exprs, const char *name)
+{
+ while (*exprs) {
+ if (strcmp((*exprs)->function, name) == 0)
+ return *exprs;
+ exprs++;
+ }
+
+ return NULL;
+}
+
+int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
+ unsigned int group)
+{
+ int i;
+ const struct aspeed_pinctrl_data *pdata =
+ pinctrl_dev_get_drvdata(pctldev);
+ const struct aspeed_pin_group *pgroup = &pdata->groups[group];
+ const struct aspeed_pin_function *pfunc =
+ &pdata->functions[function];
+
+ for (i = 0; i < pgroup->npins; i++) {
+ int pin = pgroup->pins[i];
+ const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data;
+ const struct aspeed_sig_expr *expr = NULL;
+ const struct aspeed_sig_expr **funcs;
+ const struct aspeed_sig_expr ***prios;
+
+ if (!pdesc)
+ return -EINVAL;
+
+ prios = pdesc->prios;
+
+ if (!prios)
+ continue;
+
+ /* Disable functions at a higher priority than that requested */
+ while ((funcs = *prios)) {
+ expr = aspeed_find_expr_by_name(funcs, pfunc->name);
+
+ if (expr)
+ break;
+
+ if (!aspeed_disable_sig(funcs, pdata->map))
+ return -EPERM;
+
+ prios++;
+ }
+
+ if (!expr)
+ return -EINVAL;
+
+ if (!aspeed_sig_expr_enable(expr, pdata->map))
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
+{
+ if (!exprs)
+ return false;
+
+ while (*exprs) {
+ if (strncmp((*exprs)->signal, "GPIO", 4) == 0)
+ return true;
+ exprs++;
+ }
+
+ return false;
+}
+
+int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ const struct aspeed_pinctrl_data *pdata =
+ pinctrl_dev_get_drvdata(pctldev);
+ const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
+ const struct aspeed_sig_expr ***prios, **funcs, *expr;
+
+ if (!pdesc)
+ return -EINVAL;
+
+ prios = pdesc->prios;
+
+ if (!prios)
+ return -ENXIO;
+
+ /* Disable any functions of higher priority than GPIO */
+ while ((funcs = *prios)) {
+ if (aspeed_gpio_in_exprs(funcs))
+ break;
+
+ if (!aspeed_disable_sig(funcs, pdata->map))
+ return -EPERM;
+
+ prios++;
+ }
+
+ /* No GPIO option? */
+ if (!funcs)
+ return -ENXIO;
+
+ expr = *funcs;
+
+ /*
+ * If GPIO is the "Other" case, then disabling all signal expressions
+ * is all that's required. As such it has no associated expression.
+ */
+ if (!expr)
+ return 0;
+
+ /*
+ * Otherwise, assume there is only one expression defined to enable
+ * the GPIO function
+ */
+ if (!aspeed_sig_expr_enable(expr, pdata->map))
+ return -EPERM;
+
+ return 0;
+}
+
+int aspeed_pinctrl_probe(struct platform_device *pdev,
+ struct pinctrl_desc *pdesc,
+ struct aspeed_pinctrl_data *pdata)
+{
+ struct device *parent;
+ struct pinctrl_dev *pctl;
+
+ parent = pdev->dev.parent;
+ if (!parent) {
+ dev_err(&pdev->dev, "No parent for syscon pincontroller\n");
+ return -ENODEV;
+ }
+
+ pdata->map = syscon_node_to_regmap(parent->of_node);
+ if (IS_ERR(pdata->map)) {
+ dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
+ return PTR_ERR(pdata->map);
+ }
+
+ pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
+
+ if (IS_ERR(pctl)) {
+ dev_err(&pdev->dev, "Failed to register pinctrl\n");
+ return PTR_ERR(pctl);
+ }
+
+ platform_set_drvdata(pdev, pdata);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
new file mode 100644
index 000000000000..1adb068a58ce
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -0,0 +1,562 @@
+/*
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef PINCTRL_ASPEED
+#define PINCTRL_ASPEED
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regmap.h>
+
+/*
+ * The ASPEED AST SoCs provide typically more than 200 pins for GPIO and other
+ * functions. The SoC function enabled on a pin is determined on a priority
+ * basis where a given pin can provide a number of different signal types.
+ *
+ * The signal active on a pin is described by both a priority level and
+ * compound logical expressions involving multiple operators, registers and
+ * bits. Some difficulty arises as the pin's function bit masks for each
+ * priority level are frequently not the same (i.e. cannot just flip a bit to
+ * change from a high to low priority signal), or even in the same register.
+ * Further, not all signals can be unmuxed, as some expressions depend on
+ * values in the hardware strapping register (which is treated as read-only).
+ *
+ * SoC Multi-function Pin Expression Examples
+ * ------------------------------------------
+ *
+ * Here are some sample mux configurations from the AST2400 and AST2500
+ * datasheets to illustrate the corner cases, roughly in order of least to most
+ * corner. The signal priorities are in decending order from P0 (highest).
+ *
+ * D6 is a pin with a single function (beside GPIO); a high priority signal
+ * that participates in one function:
+ *
+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ *
+ * C5 is a multi-signal pin (high and low priority signals). Here we touch
+ * different registers for the different functions that enable each signal:
+ *
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ *
+ * E19 is a single-signal pin with two functions that influence the active
+ * signal. In this case both bits have the same meaning - enable a dedicated
+ * LPC reset pin. However it's not always the case that the bits in the
+ * OR-relationship have the same meaning.
+ *
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
+ * -----+---------+-----------+-----------------------------+-----------+---------------+----------
+ *
+ * For example, pin B19 has a low-priority signal that's enabled by two
+ * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
+ * bit in the STRAP register. The ACPI bit configures signals on pins in
+ * addition to B19. Both of the low priority functions as well as the high
+ * priority function must be disabled for GPIOF1 to be used.
+ *
+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
+ * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
+ *
+ * For pin E18, the SoC ANDs the expected state of three bits to determine the
+ * pin's active signal:
+ *
+ * * SCU3C[3]: Enable external SOC reset function
+ * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
+ * * SCU90[31]: Select SPI interface CS# output
+ *
+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
+ * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
+ * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
+ *
+ * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
+ * selecting the signals on pin E18)
+ *
+ * Pin T5 is a multi-signal pin with a more complex configuration:
+ *
+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ *
+ * The high priority signal configuration is best thought of in terms of its
+ * exploded form, with reference to the SCU90[5:4] bits:
+ *
+ * * SCU90[5:4]=00: disable
+ * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
+ * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
+ * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
+ *
+ * Re-writing:
+ *
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
+ * | (SCU90[5:4]=2 & SCU84[17]=1)
+ * | (SCU90[5:4]=3 & SCU84[17]=1)
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ *
+ * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
+ * function pin", where the signal itself is determined by whether SCU94[5:4]
+ * is disabled or in one of the 18, 24 or 30bit video modes.
+ *
+ * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
+ * W1 and U5:
+ *
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
+ * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
+ * -----+---------+-----------+------------------------------+-----------+---------------+----------
+ *
+ * The examples of T5 and W1 are particularly fertile, as they also demonstrate
+ * that despite operating as part of the video input bus each signal needs to
+ * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
+ * register bit. This is a little crazy if the bus doesn't have optional
+ * signals, but is used to decent effect with some of the UARTs where not all
+ * signals are required. However, this isn't done consistently - UART1 is
+ * enabled on a per-pin basis, and by contrast, all signals for UART6 are
+ * enabled by a single bit.
+ *
+ * Further, the high and low priority signals listed in the table above share
+ * a configuration bit. The VPI signals should operate in concert in a single
+ * function, but the UART signals should retain the ability to be configured
+ * independently. This pushes the implementation down the path of tagging a
+ * signal's expressions with the function they participate in, rather than
+ * defining masks affecting multiple signals per function. The latter approach
+ * fails in this instance where applying the configuration for the UART pin of
+ * interest will stomp on the state of other UART signals when disabling the
+ * VPI functions on the current pin.
+ *
+ * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
+ * -----+------------+-----------+---------------------------+-----------+---------------+------------
+ * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
+ * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 ? Strap[6]=0 RGMII1TXCTL
+ * -----+------------+-----------+---------------------------+-----------+---------------+------------
+ *
+ * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
+ * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
+ * should be treated like any other signal type with full function expression
+ * requirements, and not assumed to be the default case. Separately, GPIOT0 and
+ * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
+ * pins in the function's group to disable the higher-priority signals such
+ * that the signal for the function of interest is correctly enabled.
+ *
+ * Finally, three priority levels aren't always enough; the AST2500 brings with
+ * it 18 pins of five priority levels, however the 18 pins only use three of
+ * the five priority levels.
+ *
+ * Ultimately the requirement to control pins in the examples above drive the
+ * design:
+ *
+ * * Pins provide signals according to functions activated in the mux
+ * configuration
+ *
+ * * Pins provide up to five signal types in a priority order
+ *
+ * * For priorities levels defined on a pin, each priority provides one signal
+ *
+ * * Enabling lower priority signals requires higher priority signals be
+ * disabled
+ *
+ * * A function represents a set of signals; functions are distinct if their
+ * sets of signals are not equal
+ *
+ * * Signals participate in one or more functions
+ *
+ * * A function is described by an expression of one or more signal
+ * descriptors, which compare bit values in a register
+ *
+ * * A signal expression is the smallest set of signal descriptors whose
+ * comparisons must evaluate 'true' for a signal to be enabled on a pin.
+ *
+ * * A function's signal is active on a pin if evaluating all signal
+ * descriptors in the pin's signal expression for the function yields a 'true'
+ * result
+ *
+ * * A signal at a given priority on a given pin is active if any of the
+ * functions in which the signal participates are active, and no higher
+ * priority signal on the pin is active
+ *
+ * * GPIO is configured per-pin
+ *
+ * And so:
+ *
+ * * To disable a signal, any function(s) activating the signal must be
+ * disabled
+ *
+ * * Each pin must know the signal expressions of functions in which it
+ * participates, for the purpose of enabling the Other function. This is done
+ * by deactivating all functions that activate higher priority signals on the
+ * pin.
+ *
+ * As a concrete example:
+ *
+ * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
+ *
+ * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
+ *
+ * * The NDCD1 signal participates in just its own NDCD1 function
+ *
+ * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
+ * prioritised
+ *
+ * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
+ * and VPI30 functions all be disabled
+ *
+ * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
+ * to provide GPIOL6
+ *
+ * Considerations
+ * --------------
+ *
+ * If pinctrl allows us to allocate a pin we can configure a function without
+ * concern for the function of already allocated pins, if pin groups are
+ * created with respect to the SoC functions in which they participate. This is
+ * intuitive, but it did not feel obvious from the bit/pin relationships.
+ *
+ * Conversely, failing to allocate all pins in a group indicates some bits (as
+ * well as pins) required for the group's configuration will already be in use,
+ * likely in a way that's inconsistent with the requirements of the failed
+ * group.
+ */
+
+/*
+ * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
+ * references registers by the device/offset mnemonic. The register macros
+ * below are named the same way to ease transcription and verification (as
+ * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
+ * reference registers beyond those dedicated to pinmux, such as the system
+ * reset control and MAC clock configuration registers. The AST2500 goes a step
+ * further and references registers in the graphics IP block, but that isn't
+ * handled yet.
+ */
+#define SCU3C 0x3C /* System Reset Control/Status Register */
+#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
+#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
+#define SCU80 0x80 /* Multi-function Pin Control #1 */
+#define SCU84 0x84 /* Multi-function Pin Control #2 */
+#define SCU88 0x88 /* Multi-function Pin Control #3 */
+#define SCU8C 0x8C /* Multi-function Pin Control #4 */
+#define SCU90 0x90 /* Multi-function Pin Control #5 */
+#define SCU94 0x94 /* Multi-function Pin Control #6 */
+#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
+#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
+#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
+#define HW_STRAP2 0xD0 /* Strapping */
+
+ /**
+ * A signal descriptor, which describes the register, bits and the
+ * enable/disable values that should be compared or written.
+ *
+ * @reg: The register offset from base in bytes
+ * @mask: The mask to apply to the register. The lowest set bit of the mask is
+ * used to derive the shift value.
+ * @enable: The value that enables the function. Value should be in the LSBs,
+ * not at the position of the mask.
+ * @disable: The value that disables the function. Value should be in the
+ * LSBs, not at the position of the mask.
+ */
+struct aspeed_sig_desc {
+ unsigned int reg;
+ u32 mask;
+ u32 enable;
+ u32 disable;
+};
+
+/**
+ * Describes a signal expression. The expression is evaluated by ANDing the
+ * evaluation of the descriptors.
+ *
+ * @signal: The signal name for the priority level on the pin
+ * @function: The name of the function the signal participates in for the
+ * associated expression
+ * @ndescs: The number of signal descriptors in the expression
+ * @descs: Pointer to an array of signal descriptors that comprise the
+ * function expression
+ */
+struct aspeed_sig_expr {
+ const char *signal;
+ const char *function;
+ int ndescs;
+ const struct aspeed_sig_desc *descs;
+};
+
+/**
+ * A struct capturing the list of expressions enabling signals at each priority
+ * for a given pin. The signal configuration for a priority level is evaluated
+ * by ORing the evaluation of the signal expressions in the respective
+ * priority's list.
+ *
+ * @name: A name for the pin
+ * @prios: A pointer to an array of expression list pointers
+ *
+ */
+struct aspeed_pin_desc {
+ const char *name;
+ const struct aspeed_sig_expr ***prios;
+};
+
+/* Macro hell */
+
+/**
+ * Short-hand macro for describing a configuration enabled by the state of one
+ * bit. The disable value is derived.
+ *
+ * @reg: The signal's associated register, offset from base
+ * @idx: The signal's bit index in the register
+ * @val: The value (0 or 1) that enables the function
+ */
+#define SIG_DESC_BIT(reg, idx, val) \
+ { reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
+
+/**
+ * A further short-hand macro describing a configuration enabled with a set bit.
+ *
+ * @reg: The configuration's associated register, offset from base
+ * @idx: The configuration's bit index in the register
+ */
+#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1)
+
+#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
+#define SIG_DESC_LIST_DECL(sig, func, ...) \
+ static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
+ { __VA_ARGS__ }
+
+#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
+#define SIG_EXPR_DECL_(sig, func) \
+ static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
+ { \
+ .signal = #sig, \
+ .function = #func, \
+ .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
+ .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
+ }
+
+/**
+ * Declare a signal expression.
+ *
+ * @sig: A macro symbol name for the signal (is subjected to stringification
+ * and token pasting)
+ * @func: The function in which the signal is participating
+ * @...: Signal descriptors that define the signal expression
+ *
+ * For example, the following declares the ROMD8 signal for the ROM16 function:
+ *
+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
+ *
+ * And with multiple signal descriptors:
+ *
+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
+ */
+#define SIG_EXPR_DECL(sig, func, ...) \
+ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
+ SIG_EXPR_DECL_(sig, func)
+
+/**
+ * Declare a pointer to a signal expression
+ *
+ * @sig: The macro symbol name for the signal (subjected to token pasting)
+ * @func: The macro symbol name for the function (subjected to token pasting)
+ */
+#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
+
+#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
+
+/**
+ * Declare a signal expression list for reference in a struct aspeed_pin_prio.
+ *
+ * @sig: A macro symbol name for the signal (is subjected to token pasting)
+ * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
+ *
+ * For example, the 16-bit ROM bus can be enabled by one of two possible signal
+ * expressions:
+ *
+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
+ * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
+ * SIG_EXPR_PTR(ROMD8, ROM16S));
+ */
+#define SIG_EXPR_LIST_DECL(sig, ...) \
+ static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
+ { __VA_ARGS__, NULL }
+
+/**
+ * A short-hand macro for declaring a function expression and an expression
+ * list with a single function.
+ *
+ * @func: A macro symbol name for the function (is subjected to token pasting)
+ * @...: Function descriptors that define the function expression
+ *
+ * For example, signal NCTS6 participates in its own function with one group:
+ *
+ * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
+ */
+#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
+ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
+ SIG_EXPR_DECL_(sig, func); \
+ SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
+
+#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
+ SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
+
+#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
+
+#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
+#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
+#define PIN_SYM(pin) pin_ ## pin
+
+#define MS_PIN_DECL_(pin, ...) \
+ static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
+ { __VA_ARGS__, NULL }; \
+ static const struct aspeed_pin_desc PIN_SYM(pin) = \
+ { #pin, PIN_EXPRS_PTR(pin) }
+
+/**
+ * Declare a multi-signal pin
+ *
+ * @pin: The pin number
+ * @other: Macro name for "other" functionality (subjected to stringification)
+ * @high: Macro name for the highest priority signal functions
+ * @low: Macro name for the low signal functions
+ *
+ * For example:
+ *
+ * #define A8 56
+ * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
+ * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+ * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
+ * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
+ * SIG_EXPR_PTR(ROMD8, ROM16S));
+ * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
+ * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
+ */
+#define MS_PIN_DECL(pin, other, high, low) \
+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
+ MS_PIN_DECL_(pin, \
+ SIG_EXPR_LIST_PTR(high), \
+ SIG_EXPR_LIST_PTR(low), \
+ SIG_EXPR_LIST_PTR(other))
+
+#define PIN_GROUP_SYM(func) pins_ ## func
+#define FUNC_GROUP_SYM(func) groups_ ## func
+#define FUNC_GROUP_DECL(func, ...) \
+ static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
+ static const char *const FUNC_GROUP_SYM(func)[] = { #func }
+
+/**
+ * Declare a single signal pin
+ *
+ * @pin: The pin number
+ * @other: Macro name for "other" functionality (subjected to stringification)
+ * @sig: Macro name for the signal (subjected to stringification)
+ *
+ * For example:
+ *
+ * #define E3 80
+ * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
+ * SS_PIN_DECL(E3, GPIOK0, SCL5);
+ */
+#define SS_PIN_DECL(pin, other, sig) \
+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
+ MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
+
+/**
+ * Single signal, single function pin declaration
+ *
+ * @pin: The pin number
+ * @other: Macro name for "other" functionality (subjected to stringification)
+ * @sig: Macro name for the signal (subjected to stringification)
+ * @...: Signal descriptors that define the function expression
+ *
+ * For example:
+ *
+ * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
+ */
+#define SSSF_PIN_DECL(pin, other, sig, ...) \
+ SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
+ SIG_EXPR_LIST_DECL_SINGLE(other, other); \
+ MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
+ FUNC_GROUP_DECL(sig, pin)
+
+struct aspeed_pinctrl_data {
+ struct regmap *map;
+
+ const struct pinctrl_pin_desc *pins;
+ const unsigned int npins;
+
+ const struct aspeed_pin_group *groups;
+ const unsigned int ngroups;
+
+ const struct aspeed_pin_function *functions;
+ const unsigned int nfunctions;
+};
+
+#define ASPEED_PINCTRL_PIN(name_) \
+ [name_] = { \
+ .number = name_, \
+ .name = #name_, \
+ .drv_data = (void *) &(PIN_SYM(name_)) \
+ }
+
+struct aspeed_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ const unsigned int npins;
+};
+
+#define ASPEED_PINCTRL_GROUP(name_) { \
+ .name = #name_, \
+ .pins = &(PIN_GROUP_SYM(name_))[0], \
+ .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
+}
+
+struct aspeed_pin_function {
+ const char *name;
+ const char *const *groups;
+ unsigned int ngroups;
+};
+
+#define ASPEED_PINCTRL_FUNC(name_, ...) { \
+ .name = #name_, \
+ .groups = &FUNC_GROUP_SYM(name_)[0], \
+ .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
+}
+
+int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
+const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group);
+int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group, const unsigned int **pins,
+ unsigned int *npins);
+void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int offset);
+int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
+const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
+ unsigned int function);
+int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
+ unsigned int function, const char * const **groups,
+ unsigned int * const num_groups);
+int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
+ unsigned int group);
+int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset);
+int aspeed_pinctrl_probe(struct platform_device *pdev,
+ struct pinctrl_desc *pdesc,
+ struct aspeed_pinctrl_data *pdata);
+
+#endif /* PINCTRL_ASPEED */
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
` (8 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
A subset of the pins and functions are exposed. The selection of
functions and pins is driven by the development of OpenBMC[1] on the
AST2400 SoC, particularly around booting the OpenPOWER Palmetto
development machine.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/mach-aspeed/Kconfig | 1 +
drivers/pinctrl/aspeed/Kconfig | 8 +
drivers/pinctrl/aspeed/Makefile | 1 +
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1091 ++++++++++++++++++++++++++++
4 files changed, 1101 insertions(+)
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index 632899c58098..2589b90b0a7b 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -15,6 +15,7 @@ config MACH_ASPEED_G4
bool "Aspeed SoC 4th Generation"
depends on ARCH_MULTI_V5
select CPU_ARM926T
+ select PINCTRL_ASPEED_G4
help
Say yes if you intend to run on an Aspeed ast2400 or similar
fourth generation BMCs, such as those used by OpenPower Power8
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
index 34d9050f2761..480a206c69f1 100644
--- a/drivers/pinctrl/aspeed/Kconfig
+++ b/drivers/pinctrl/aspeed/Kconfig
@@ -6,3 +6,11 @@ config PINCTRL_ASPEED
select GENERIC_PINCONF
select MFD_SYSCON
select REGMAP_MMIO
+
+config PINCTRL_ASPEED_G4
+ bool "Aspeed AST G4 SoC pin control"
+ depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF
+ select PINCTRL_ASPEED
+ help
+ Say Y here to enable pin controller support for Aspeed's 4th
+ generation AST SoCs. GPIO is provided by a separate GPIO driver.
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
index 6bc001c001ee..253bddd1fc2d 100644
--- a/drivers/pinctrl/aspeed/Makefile
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -1,3 +1,4 @@
# Aspeed pinctrl support
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
+obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
new file mode 100644
index 000000000000..84f95a6ab8d1
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -0,0 +1,1091 @@
+/*
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-aspeed.h"
+
+/*
+ * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK,
+ * TIMER3 etc.
+ *
+ * Pins are defined in GPIO bank order:
+ *
+ * GPIOA0: 0
+ * ...
+ * GPIOA7: 7
+ * GPIOB0: 8
+ * ...
+ * GPIOZ7: 207
+ * GPIOAA0: 208
+ * ...
+ * GPIOAB3: 219
+ *
+ * Not all pins have their signals defined (yet).
+ */
+
+#define A4 2
+SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
+
+#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
+
+#define C5 4
+SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
+MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5);
+
+FUNC_GROUP_DECL(TIMER5, C5);
+
+#define B4 5
+SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
+MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6);
+
+FUNC_GROUP_DECL(TIMER6, B4);
+FUNC_GROUP_DECL(I2C9, C5, B4);
+
+#define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
+
+#define A3 6
+SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
+MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7);
+
+FUNC_GROUP_DECL(TIMER7, A3);
+
+#define D5 7
+SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
+MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8);
+
+FUNC_GROUP_DECL(TIMER8, D5);
+FUNC_GROUP_DECL(MDIO2, A3, D5);
+
+#define H19 13
+#define H19_DESC SIG_DESC_SET(SCU80, 13)
+SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC);
+MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI);
+
+FUNC_GROUP_DECL(LPCPD, H19);
+FUNC_GROUP_DECL(LPCSMI, H19);
+
+#define H20 14
+SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
+
+#define SD1_DESC SIG_DESC_SET(SCU90, 0)
+#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
+
+#define C4 16
+SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
+MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10);
+
+#define B3 17
+SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
+MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10);
+
+FUNC_GROUP_DECL(I2C10, C4, B3);
+
+#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
+
+#define A2 18
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
+MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11);
+
+#define E5 19
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
+MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11);
+
+FUNC_GROUP_DECL(I2C11, A2, E5);
+
+#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
+
+#define D4 20
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
+MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12);
+
+#define C3 21
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
+MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12);
+
+FUNC_GROUP_DECL(I2C12, D4, C3);
+
+#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
+
+#define B2 22
+SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
+MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13);
+
+#define A1 23
+SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
+MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13);
+
+FUNC_GROUP_DECL(I2C13, B2, A1);
+FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
+
+#define SD2_DESC SIG_DESC_SET(SCU90, 1)
+#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
+#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
+
+#define A18 24
+SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
+MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN);
+
+#define D16 25
+SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
+MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT);
+
+FUNC_GROUP_DECL(GPID0, A18, D16);
+
+#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
+#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
+
+#define D15 32
+SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
+SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
+SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
+MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN);
+
+FUNC_GROUP_DECL(NCTS3, D15);
+
+#define C15 33
+SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
+SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
+SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
+MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT);
+
+FUNC_GROUP_DECL(NDCD3, C15);
+FUNC_GROUP_DECL(GPIE0, D15, C15);
+
+#define D18 40
+SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24));
+
+#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0)
+
+#define B19 41
+SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
+SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12));
+SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
+MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI);
+FUNC_GROUP_DECL(NDCD4, B19);
+FUNC_GROUP_DECL(SIOPBI, B19);
+
+#define D17 43
+SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
+SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
+SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
+MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO);
+FUNC_GROUP_DECL(NRI4, D17);
+FUNC_GROUP_DECL(SIOPBO, D17);
+
+FUNC_GROUP_DECL(ACPI, B19, D17);
+
+#define E16 46
+SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
+
+#define C17 47
+SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
+
+#define AA22 54
+SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
+
+#define U18 55
+SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
+
+#define UART6_DESC SIG_DESC_SET(SCU90, 7)
+#define ROM16_DESC SIG_DESC_SET(SCU90, 6)
+#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
+#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 }
+
+#define A8 56
+SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC);
+MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
+
+#define C7 57
+SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC);
+MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6);
+
+#define B7 58
+SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC);
+MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6);
+
+#define A7 59
+SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC);
+MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6);
+
+#define D7 60
+SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC);
+MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6);
+
+#define B6 61
+SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC);
+MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6);
+
+#define A6 62
+SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC);
+MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6);
+
+#define E7 63
+SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC);
+SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
+SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S);
+SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC);
+MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6);
+
+FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
+
+#define J3 75
+SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
+
+#define T4 76
+SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12));
+
+#define U2 77
+SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13));
+
+#define T2 78
+SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14));
+
+#define T1 79
+SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
+
+#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
+
+#define E3 80
+SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
+SS_PIN_DECL(E3, GPIOK0, SCL5);
+
+#define D2 81
+SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
+SS_PIN_DECL(D2, GPIOK1, SDA5);
+
+FUNC_GROUP_DECL(I2C5, E3, D2);
+
+#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
+
+#define C1 82
+SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
+SS_PIN_DECL(C1, GPIOK2, SCL6);
+
+#define F4 83
+SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
+SS_PIN_DECL(F4, GPIOK3, SDA6);
+
+FUNC_GROUP_DECL(I2C6, C1, F4);
+
+#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
+
+#define E2 84
+SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
+SS_PIN_DECL(E2, GPIOK4, SCL7);
+
+#define D1 85
+SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
+SS_PIN_DECL(D1, GPIOK5, SDA7);
+
+FUNC_GROUP_DECL(I2C7, E2, D1);
+
+#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
+
+#define G5 86
+SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
+SS_PIN_DECL(G5, GPIOK6, SCL8);
+
+#define F3 87
+SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
+SS_PIN_DECL(F3, GPIOK7, SDA8);
+
+FUNC_GROUP_DECL(I2C8, G5, F3);
+
+#define U1 88
+SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
+
+#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 }
+#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
+#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 }
+
+#define T5 89
+#define T5_DESC SIG_DESC_SET(SCU84, 17)
+SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC);
+SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC);
+SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC);
+SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18),
+ SIG_EXPR_PTR(VPIDE, VPI24),
+ SIG_EXPR_PTR(VPIDE, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC);
+MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1);
+FUNC_GROUP_DECL(NDCD1, T5);
+
+#define U3 90
+#define U3_DESC SIG_DESC_SET(SCU84, 18)
+SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC);
+SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC);
+SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC);
+SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18),
+ SIG_EXPR_PTR(VPIODD, VPI24),
+ SIG_EXPR_PTR(VPIODD, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC);
+MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1);
+FUNC_GROUP_DECL(NDSR1, U3);
+
+#define V1 91
+#define V1_DESC SIG_DESC_SET(SCU84, 19)
+SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC);
+SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC);
+SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC);
+SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18),
+ SIG_EXPR_PTR(VPIHS, VPI24),
+ SIG_EXPR_PTR(VPIHS, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC);
+MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1);
+FUNC_GROUP_DECL(NRI1, V1);
+
+#define U4 92
+#define U4_DESC SIG_DESC_SET(SCU84, 20)
+SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC);
+SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC);
+SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC);
+SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18),
+ SIG_EXPR_PTR(VPIVS, VPI24),
+ SIG_EXPR_PTR(VPIVS, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC);
+MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1);
+FUNC_GROUP_DECL(NDTR1, U4);
+
+#define V2 93
+#define V2_DESC SIG_DESC_SET(SCU84, 21)
+SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC);
+SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC);
+SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC);
+SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18),
+ SIG_EXPR_PTR(VPICLK, VPI24),
+ SIG_EXPR_PTR(VPICLK, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC);
+MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1);
+FUNC_GROUP_DECL(NRTS1, V2);
+
+#define W1 94
+#define W1_DESC SIG_DESC_SET(SCU84, 22)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC);
+MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1);
+FUNC_GROUP_DECL(TXD1, W1);
+
+#define U5 95
+#define U5_DESC SIG_DESC_SET(SCU84, 23)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC);
+MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1);
+FUNC_GROUP_DECL(RXD1, U5);
+
+#define W4 104
+#define W4_DESC SIG_DESC_SET(SCU88, 0)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC);
+MS_PIN_DECL(W4, GPION0, VPIG0, PWM0);
+FUNC_GROUP_DECL(PWM0, W4);
+
+#define Y3 105
+#define Y3_DESC SIG_DESC_SET(SCU88, 1)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC);
+MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1);
+FUNC_GROUP_DECL(PWM1, Y3);
+
+#define AA2 106
+#define AA2_DESC SIG_DESC_SET(SCU88, 2)
+SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC);
+SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC);
+SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC);
+SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18),
+ SIG_EXPR_PTR(VPIG2, VPI24),
+ SIG_EXPR_PTR(VPIG2, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC);
+MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2);
+FUNC_GROUP_DECL(PWM2, AA2);
+
+#define AB1 107
+#define AB1_DESC SIG_DESC_SET(SCU88, 3)
+SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC);
+SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC);
+SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC);
+SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18),
+ SIG_EXPR_PTR(VPIG2, VPI24),
+ SIG_EXPR_PTR(VPIG2, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC);
+MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3);
+FUNC_GROUP_DECL(PWM3, AB1);
+
+#define W5 108
+#define W5_DESC SIG_DESC_SET(SCU88, 4)
+SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC);
+SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC);
+SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC);
+SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18),
+ SIG_EXPR_PTR(VPIG2, VPI24),
+ SIG_EXPR_PTR(VPIG2, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC);
+MS_PIN_DECL(W5, GPION4, VPIG4, PWM4);
+FUNC_GROUP_DECL(PWM4, W5);
+
+#define Y4 109
+#define Y4_DESC SIG_DESC_SET(SCU88, 5)
+SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC);
+SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC);
+SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC);
+SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18),
+ SIG_EXPR_PTR(VPIG2, VPI24),
+ SIG_EXPR_PTR(VPIG2, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC);
+MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5);
+FUNC_GROUP_DECL(PWM5, Y4);
+
+#define AA3 110
+#define AA3_DESC SIG_DESC_SET(SCU88, 6)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC);
+MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6);
+FUNC_GROUP_DECL(PWM6, AA3);
+
+#define AB2 111
+#define AB2_DESC SIG_DESC_SET(SCU88, 7)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC);
+MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7);
+FUNC_GROUP_DECL(PWM7, AB2);
+
+#define V6 112
+SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8));
+SS_PIN_DECL(V6, GPIOO0, VPIG8);
+
+#define Y5 113
+SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
+SS_PIN_DECL(Y5, GPIOO1, VPIG9);
+
+FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2);
+FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5);
+FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3,
+ AB2);
+
+#define Y7 125
+SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5);
+MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5));
+
+#define AA7 126
+SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22));
+
+#define AB7 127
+SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23));
+
+#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
+
+#define D3 128
+SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
+SS_PIN_DECL(D3, GPIOQ0, SCL3);
+
+#define C2 129
+SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
+SS_PIN_DECL(C2, GPIOQ1, SDA3);
+
+FUNC_GROUP_DECL(I2C3, D3, C2);
+
+#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
+
+#define B1 130
+SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
+SS_PIN_DECL(B1, GPIOQ2, SCL4);
+
+#define F5 131
+SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
+SS_PIN_DECL(F5, GPIOQ3, SDA4);
+
+FUNC_GROUP_DECL(I2C4, B1, F5);
+
+#define DASH9028_DESC SIG_DESC_SET(SCU90, 28)
+
+#define H2 134
+SSSF_PIN_DECL(H2, GPIOQ6, DASHH2, DASH9028_DESC);
+
+#define H1 135
+SSSF_PIN_DECL(H1, GPIOQ7, DASHH1, DASH9028_DESC);
+
+#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 }
+#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 }
+#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 }
+#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 }
+#define VPO_OFF_12 { SCU94, 0x2, 0, 0 }
+#define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
+
+#define V20 136
+#define V20_DESC SIG_DESC_SET(SCU88, 24)
+SIG_EXPR_LIST_DECL_SINGLE(GPIOR0, GPIOR0);
+SIG_EXPR_DECL(ROMCS1, ROM8, V20_DESC);
+SIG_EXPR_DECL(ROMCS1, ROM16, V20_DESC);
+SIG_EXPR_DECL(ROMCS1, ROM16S, V20_DESC);
+SIG_EXPR_LIST_DECL(ROMCS1, SIG_EXPR_PTR(ROMCS1, ROM8),
+ SIG_EXPR_PTR(ROMCS1, ROM16),
+ SIG_EXPR_PTR(ROMCS1, ROM16S));
+MS_PIN_DECL_(V20, SIG_EXPR_LIST_PTR(ROMCS1), SIG_EXPR_LIST_PTR(GPIOR0));
+
+#define U21 144
+#define U21_DESC SIG_DESC_SET(SCU8C, 0)
+SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL(ROMD4, SIG_EXPR_PTR(ROMD4, ROM8),
+ SIG_EXPR_PTR(ROMD4, ROM16),
+ SIG_EXPR_PTR(ROMD4, ROM16S));
+SIG_EXPR_DECL(VPODE, VPO12, U21_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPODE, VPO24, U21_DESC, VPO12_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPODE, VPO12, VPO24);
+MS_PIN_DECL(U21, GPIOS0, ROMD4, VPODE);
+
+#define T19 145
+#define T19_DESC SIG_DESC_SET(SCU8C, 1)
+SIG_EXPR_DECL(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL(ROMD5, SIG_EXPR_PTR(ROMD5, ROM8),
+ SIG_EXPR_PTR(ROMD5, ROM16),
+ SIG_EXPR_PTR(ROMD5, ROM16S));
+SIG_EXPR_DECL(VPOHS, VPO12, T19_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOHS, VPO24, T19_DESC, VPO24_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOHS, VPO12, VPO24);
+MS_PIN_DECL(T19, GPIOS1, ROMD5, VPOHS);
+
+#define V22 146
+#define V22_DESC SIG_DESC_SET(SCU8C, 2)
+SIG_EXPR_DECL(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL(ROMD6, SIG_EXPR_PTR(ROMD6, ROM8),
+ SIG_EXPR_PTR(ROMD6, ROM16),
+ SIG_EXPR_PTR(ROMD6, ROM16S));
+SIG_EXPR_DECL(VPOVS, VPO12, V22_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOVS, VPO24, V22_DESC, VPO24_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOVS, VPO12, VPO24);
+MS_PIN_DECL(V22, GPIOS2, ROMD6, VPOVS);
+
+#define U20 147
+#define U20_DESC SIG_DESC_SET(SCU8C, 3)
+SIG_EXPR_DECL(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL(ROMD7, SIG_EXPR_PTR(ROMD7, ROM8),
+ SIG_EXPR_PTR(ROMD7, ROM16),
+ SIG_EXPR_PTR(ROMD7, ROM16S));
+SIG_EXPR_DECL(VPOCLK, VPO12, U20_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOCLK, VPO24, U20_DESC, VPO24_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOCLK, VPO12, VPO24);
+MS_PIN_DECL(U20, GPIOS3, ROMD7, VPOCLK);
+
+#define R18 148
+#define ROMOE_DESC SIG_DESC_SET(SCU8C, 4)
+SIG_EXPR_LIST_DECL_SINGLE(GPIOS4, GPIOS4);
+SIG_EXPR_DECL(ROMOE, ROM8, ROMOE_DESC);
+SIG_EXPR_DECL(ROMOE, ROM16, ROMOE_DESC);
+SIG_EXPR_DECL(ROMOE, ROM16S, ROMOE_DESC);
+SIG_EXPR_LIST_DECL(ROMOE, SIG_EXPR_PTR(ROMOE, ROM8),
+ SIG_EXPR_PTR(ROMOE, ROM16),
+ SIG_EXPR_PTR(ROMOE, ROM16S));
+MS_PIN_DECL_(R18, SIG_EXPR_LIST_PTR(ROMOE), SIG_EXPR_LIST_PTR(GPIOS4));
+
+#define N21 149
+#define ROMWE_DESC SIG_DESC_SET(SCU8C, 5)
+SIG_EXPR_LIST_DECL_SINGLE(GPIOS5, GPIOS5);
+SIG_EXPR_DECL(ROMWE, ROM8, ROMWE_DESC);
+SIG_EXPR_DECL(ROMWE, ROM16, ROMWE_DESC);
+SIG_EXPR_DECL(ROMWE, ROM16S, ROMWE_DESC);
+SIG_EXPR_LIST_DECL(ROMWE, SIG_EXPR_PTR(ROMWE, ROM8),
+ SIG_EXPR_PTR(ROMWE, ROM16),
+ SIG_EXPR_PTR(ROMWE, ROM16S));
+MS_PIN_DECL_(N21, SIG_EXPR_LIST_PTR(ROMWE), SIG_EXPR_LIST_PTR(GPIOS5));
+
+#define L22 150
+#define L22_DESC SIG_DESC_SET(SCU8C, 6)
+SIG_EXPR_DECL(ROMA22, ROM8, L22_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA22, ROM16, L22_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA22, ROM16S, L22_DESC, VPO_OFF_12);
+SIG_EXPR_LIST_DECL(ROMA22, SIG_EXPR_PTR(ROMA22, ROM8),
+ SIG_EXPR_PTR(ROMA22, ROM16),
+ SIG_EXPR_PTR(ROMA22, ROM16S));
+SIG_EXPR_LIST_DECL_SINGLE(VPOR4, VPO24, L22_DESC, VPO_24_OFF);
+MS_PIN_DECL(L22, GPIOS6, ROMA22, VPOR4);
+
+#define K18 151
+#define K18_DESC SIG_DESC_SET(SCU8C, 7)
+SIG_EXPR_DECL(ROMA23, ROM8, K18_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA23, ROM16, K18_DESC, VPO_OFF_12);
+SIG_EXPR_DECL(ROMA23, ROM16S, K18_DESC, VPO_OFF_12);
+SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8),
+ SIG_EXPR_PTR(ROMA23, ROM16),
+ SIG_EXPR_PTR(ROMA23, ROM16S));
+SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF);
+MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5);
+
+FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18);
+FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
+ A8, C7, B7, A7, D7, B6, A6, E7);
+FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20);
+FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18);
+
+#define RMII1_DESC { HW_STRAP1, BIT(6), 0, 0 }
+
+#define A12 152
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
+MS_PIN_DECL_(A12, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1TXEN),
+ SIG_EXPR_LIST_PTR(RGMII1TXCK));
+
+#define B12 153
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
+SIG_EXPR_LIST_DECL_SINGLE(DASHB12, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
+MS_PIN_DECL_(B12, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(DASHB12),
+ SIG_EXPR_LIST_PTR(RGMII1TXCTL));
+
+#define C12 154
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
+MS_PIN_DECL_(C12, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
+ SIG_EXPR_LIST_PTR(RGMII1TXD0));
+
+#define D12 155
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
+MS_PIN_DECL_(D12, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
+ SIG_EXPR_LIST_PTR(RGMII1TXD1));
+
+#define E12 156
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
+SIG_EXPR_LIST_DECL_SINGLE(DASHE12, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
+MS_PIN_DECL_(E12, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(DASHE12),
+ SIG_EXPR_LIST_PTR(RGMII1TXD2));
+
+#define A13 157
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
+SIG_EXPR_LIST_DECL_SINGLE(DASHA13, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
+MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13),
+ SIG_EXPR_LIST_PTR(RGMII1TXD3));
+
+#define E11 164
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
+MS_PIN_DECL_(E11, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLK),
+ SIG_EXPR_LIST_PTR(RGMII1RXCK));
+
+#define D11 165
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
+SIG_EXPR_LIST_DECL_SINGLE(DASHD11, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
+MS_PIN_DECL_(D11, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(DASHD11),
+ SIG_EXPR_LIST_PTR(RGMII1RXCTL));
+
+#define C11 166
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
+MS_PIN_DECL_(C11, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
+ SIG_EXPR_LIST_PTR(RGMII1RXD0));
+
+#define B11 167
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
+MS_PIN_DECL_(B11, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
+ SIG_EXPR_LIST_PTR(RGMII1RXD1));
+
+#define A11 168
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
+MS_PIN_DECL_(A11, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
+ SIG_EXPR_LIST_PTR(RGMII1RXD2));
+
+#define E10 169
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
+MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
+ SIG_EXPR_LIST_PTR(RGMII1RXD3));
+
+FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
+ E10);
+FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
+ E10);
+
+/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
+ * pins becomes 220.
+ */
+#define ASPEED_G4_NR_PINS 220
+
+static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
+ ASPEED_PINCTRL_PIN(A4),
+ ASPEED_PINCTRL_PIN(C5),
+ ASPEED_PINCTRL_PIN(B4),
+ ASPEED_PINCTRL_PIN(A3),
+ ASPEED_PINCTRL_PIN(D5),
+ ASPEED_PINCTRL_PIN(H19),
+ ASPEED_PINCTRL_PIN(H20),
+ ASPEED_PINCTRL_PIN(C4),
+ ASPEED_PINCTRL_PIN(B3),
+ ASPEED_PINCTRL_PIN(A2),
+ ASPEED_PINCTRL_PIN(E5),
+ ASPEED_PINCTRL_PIN(D4),
+ ASPEED_PINCTRL_PIN(C3),
+ ASPEED_PINCTRL_PIN(B2),
+ ASPEED_PINCTRL_PIN(A1),
+ ASPEED_PINCTRL_PIN(A18),
+ ASPEED_PINCTRL_PIN(D16),
+ ASPEED_PINCTRL_PIN(D15),
+ ASPEED_PINCTRL_PIN(C15),
+ ASPEED_PINCTRL_PIN(D18),
+ ASPEED_PINCTRL_PIN(B19),
+ ASPEED_PINCTRL_PIN(D17),
+ ASPEED_PINCTRL_PIN(E16),
+ ASPEED_PINCTRL_PIN(C17),
+ ASPEED_PINCTRL_PIN(AA22),
+ ASPEED_PINCTRL_PIN(U18),
+ ASPEED_PINCTRL_PIN(A8),
+ ASPEED_PINCTRL_PIN(C7),
+ ASPEED_PINCTRL_PIN(B7),
+ ASPEED_PINCTRL_PIN(A7),
+ ASPEED_PINCTRL_PIN(D7),
+ ASPEED_PINCTRL_PIN(B6),
+ ASPEED_PINCTRL_PIN(A6),
+ ASPEED_PINCTRL_PIN(E7),
+ ASPEED_PINCTRL_PIN(J3),
+ ASPEED_PINCTRL_PIN(T4),
+ ASPEED_PINCTRL_PIN(U2),
+ ASPEED_PINCTRL_PIN(T2),
+ ASPEED_PINCTRL_PIN(T1),
+ ASPEED_PINCTRL_PIN(E3),
+ ASPEED_PINCTRL_PIN(D2),
+ ASPEED_PINCTRL_PIN(C1),
+ ASPEED_PINCTRL_PIN(F4),
+ ASPEED_PINCTRL_PIN(E2),
+ ASPEED_PINCTRL_PIN(D1),
+ ASPEED_PINCTRL_PIN(G5),
+ ASPEED_PINCTRL_PIN(F3),
+ ASPEED_PINCTRL_PIN(U1),
+ ASPEED_PINCTRL_PIN(T5),
+ ASPEED_PINCTRL_PIN(U3),
+ ASPEED_PINCTRL_PIN(V1),
+ ASPEED_PINCTRL_PIN(U4),
+ ASPEED_PINCTRL_PIN(V2),
+ ASPEED_PINCTRL_PIN(W1),
+ ASPEED_PINCTRL_PIN(U5),
+ ASPEED_PINCTRL_PIN(W4),
+ ASPEED_PINCTRL_PIN(Y3),
+ ASPEED_PINCTRL_PIN(AA2),
+ ASPEED_PINCTRL_PIN(AB1),
+ ASPEED_PINCTRL_PIN(W5),
+ ASPEED_PINCTRL_PIN(Y4),
+ ASPEED_PINCTRL_PIN(AA3),
+ ASPEED_PINCTRL_PIN(AB2),
+ ASPEED_PINCTRL_PIN(V6),
+ ASPEED_PINCTRL_PIN(Y5),
+ ASPEED_PINCTRL_PIN(Y7),
+ ASPEED_PINCTRL_PIN(AA7),
+ ASPEED_PINCTRL_PIN(AB7),
+ ASPEED_PINCTRL_PIN(D3),
+ ASPEED_PINCTRL_PIN(C2),
+ ASPEED_PINCTRL_PIN(B1),
+ ASPEED_PINCTRL_PIN(F5),
+ ASPEED_PINCTRL_PIN(H2),
+ ASPEED_PINCTRL_PIN(H1),
+ ASPEED_PINCTRL_PIN(V20),
+ ASPEED_PINCTRL_PIN(U21),
+ ASPEED_PINCTRL_PIN(T19),
+ ASPEED_PINCTRL_PIN(V22),
+ ASPEED_PINCTRL_PIN(U20),
+ ASPEED_PINCTRL_PIN(R18),
+ ASPEED_PINCTRL_PIN(N21),
+ ASPEED_PINCTRL_PIN(L22),
+ ASPEED_PINCTRL_PIN(K18),
+ ASPEED_PINCTRL_PIN(A12),
+ ASPEED_PINCTRL_PIN(B12),
+ ASPEED_PINCTRL_PIN(C12),
+ ASPEED_PINCTRL_PIN(D12),
+ ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(A13),
+ ASPEED_PINCTRL_PIN(E11),
+ ASPEED_PINCTRL_PIN(D11),
+ ASPEED_PINCTRL_PIN(C11),
+ ASPEED_PINCTRL_PIN(B11),
+ ASPEED_PINCTRL_PIN(A11),
+ ASPEED_PINCTRL_PIN(E10),
+};
+
+static const struct aspeed_pin_group aspeed_g4_groups[] = {
+ ASPEED_PINCTRL_GROUP(TIMER3),
+ ASPEED_PINCTRL_GROUP(I2C9),
+ ASPEED_PINCTRL_GROUP(TIMER5),
+ ASPEED_PINCTRL_GROUP(TIMER6),
+ ASPEED_PINCTRL_GROUP(MDIO2),
+ ASPEED_PINCTRL_GROUP(LPCPD),
+ ASPEED_PINCTRL_GROUP(LPCSMI),
+ ASPEED_PINCTRL_GROUP(LPCPME),
+ ASPEED_PINCTRL_GROUP(TIMER7),
+ ASPEED_PINCTRL_GROUP(TIMER8),
+ ASPEED_PINCTRL_GROUP(SD1),
+ ASPEED_PINCTRL_GROUP(GPID0),
+ ASPEED_PINCTRL_GROUP(I2C10),
+ ASPEED_PINCTRL_GROUP(I2C11),
+ ASPEED_PINCTRL_GROUP(I2C12),
+ ASPEED_PINCTRL_GROUP(I2C13),
+ ASPEED_PINCTRL_GROUP(NCTS3),
+ ASPEED_PINCTRL_GROUP(NDCD3),
+ ASPEED_PINCTRL_GROUP(GPIE0),
+ ASPEED_PINCTRL_GROUP(NCTS4),
+ ASPEED_PINCTRL_GROUP(ACPI),
+ ASPEED_PINCTRL_GROUP(NDCD4),
+ ASPEED_PINCTRL_GROUP(SIOPBI),
+ ASPEED_PINCTRL_GROUP(NRI4),
+ ASPEED_PINCTRL_GROUP(SIOPBO),
+ ASPEED_PINCTRL_GROUP(TXD4),
+ ASPEED_PINCTRL_GROUP(RXD4),
+ ASPEED_PINCTRL_GROUP(FLBUSY),
+ ASPEED_PINCTRL_GROUP(FLWP),
+ ASPEED_PINCTRL_GROUP(UART6),
+ ASPEED_PINCTRL_GROUP(SGPMI),
+ ASPEED_PINCTRL_GROUP(VGAHS),
+ ASPEED_PINCTRL_GROUP(VGAVS),
+ ASPEED_PINCTRL_GROUP(DDCCLK),
+ ASPEED_PINCTRL_GROUP(DDCDAT),
+ ASPEED_PINCTRL_GROUP(I2C5),
+ ASPEED_PINCTRL_GROUP(I2C6),
+ ASPEED_PINCTRL_GROUP(I2C7),
+ ASPEED_PINCTRL_GROUP(I2C8),
+ ASPEED_PINCTRL_GROUP(NCTS1),
+ ASPEED_PINCTRL_GROUP(NDCD1),
+ ASPEED_PINCTRL_GROUP(NDSR1),
+ ASPEED_PINCTRL_GROUP(NRI1),
+ ASPEED_PINCTRL_GROUP(NDTR1),
+ ASPEED_PINCTRL_GROUP(NRTS1),
+ ASPEED_PINCTRL_GROUP(TXD1),
+ ASPEED_PINCTRL_GROUP(RXD1),
+ ASPEED_PINCTRL_GROUP(PWM0),
+ ASPEED_PINCTRL_GROUP(PWM1),
+ ASPEED_PINCTRL_GROUP(PWM2),
+ ASPEED_PINCTRL_GROUP(PWM3),
+ ASPEED_PINCTRL_GROUP(PWM4),
+ ASPEED_PINCTRL_GROUP(PWM5),
+ ASPEED_PINCTRL_GROUP(PWM6),
+ ASPEED_PINCTRL_GROUP(PWM7),
+ ASPEED_PINCTRL_GROUP(VPI18),
+ ASPEED_PINCTRL_GROUP(VPI24),
+ ASPEED_PINCTRL_GROUP(VPI30),
+ ASPEED_PINCTRL_GROUP(BMCINT),
+ ASPEED_PINCTRL_GROUP(FLACK),
+ ASPEED_PINCTRL_GROUP(I2C3),
+ ASPEED_PINCTRL_GROUP(I2C4),
+ ASPEED_PINCTRL_GROUP(DASHH2),
+ ASPEED_PINCTRL_GROUP(DASHH1),
+ ASPEED_PINCTRL_GROUP(ROM8),
+ ASPEED_PINCTRL_GROUP(ROM16),
+ ASPEED_PINCTRL_GROUP(VPO12),
+ ASPEED_PINCTRL_GROUP(VPO24),
+ ASPEED_PINCTRL_GROUP(RGMII1),
+ ASPEED_PINCTRL_GROUP(RMII1),
+};
+
+static const struct aspeed_pin_function aspeed_g4_functions[] = {
+ ASPEED_PINCTRL_FUNC(TIMER3),
+ ASPEED_PINCTRL_FUNC(I2C9),
+ ASPEED_PINCTRL_FUNC(TIMER5),
+ ASPEED_PINCTRL_FUNC(TIMER6),
+ ASPEED_PINCTRL_FUNC(MDIO2),
+ ASPEED_PINCTRL_FUNC(LPCPD),
+ ASPEED_PINCTRL_FUNC(LPCSMI),
+ ASPEED_PINCTRL_FUNC(TIMER7),
+ ASPEED_PINCTRL_FUNC(TIMER8),
+ ASPEED_PINCTRL_FUNC(SD1),
+ ASPEED_PINCTRL_FUNC(GPID0),
+ ASPEED_PINCTRL_FUNC(I2C10),
+ ASPEED_PINCTRL_FUNC(I2C11),
+ ASPEED_PINCTRL_FUNC(I2C12),
+ ASPEED_PINCTRL_FUNC(I2C13),
+ ASPEED_PINCTRL_FUNC(NCTS3),
+ ASPEED_PINCTRL_FUNC(NDCD3),
+ ASPEED_PINCTRL_FUNC(GPIE0),
+ ASPEED_PINCTRL_FUNC(NCTS4),
+ ASPEED_PINCTRL_FUNC(ACPI),
+ ASPEED_PINCTRL_FUNC(NDCD4),
+ ASPEED_PINCTRL_FUNC(SIOPBI),
+ ASPEED_PINCTRL_FUNC(NRI4),
+ ASPEED_PINCTRL_FUNC(SIOPBO),
+ ASPEED_PINCTRL_FUNC(TXD4),
+ ASPEED_PINCTRL_FUNC(RXD4),
+ ASPEED_PINCTRL_FUNC(FLBUSY),
+ ASPEED_PINCTRL_FUNC(FLWP),
+ ASPEED_PINCTRL_FUNC(UART6),
+ ASPEED_PINCTRL_FUNC(SGPMI),
+ ASPEED_PINCTRL_FUNC(VGAHS),
+ ASPEED_PINCTRL_FUNC(VGAVS),
+ ASPEED_PINCTRL_FUNC(DDCCLK),
+ ASPEED_PINCTRL_FUNC(DDCDAT),
+ ASPEED_PINCTRL_FUNC(I2C5),
+ ASPEED_PINCTRL_FUNC(I2C6),
+ ASPEED_PINCTRL_FUNC(I2C7),
+ ASPEED_PINCTRL_FUNC(I2C8),
+ ASPEED_PINCTRL_FUNC(NCTS1),
+ ASPEED_PINCTRL_FUNC(NDCD1),
+ ASPEED_PINCTRL_FUNC(NDSR1),
+ ASPEED_PINCTRL_FUNC(NRI1),
+ ASPEED_PINCTRL_FUNC(NDTR1),
+ ASPEED_PINCTRL_FUNC(NRTS1),
+ ASPEED_PINCTRL_FUNC(TXD1),
+ ASPEED_PINCTRL_FUNC(RXD1),
+ ASPEED_PINCTRL_FUNC(PWM0),
+ ASPEED_PINCTRL_FUNC(PWM1),
+ ASPEED_PINCTRL_FUNC(PWM2),
+ ASPEED_PINCTRL_FUNC(PWM3),
+ ASPEED_PINCTRL_FUNC(PWM4),
+ ASPEED_PINCTRL_FUNC(PWM5),
+ ASPEED_PINCTRL_FUNC(PWM6),
+ ASPEED_PINCTRL_FUNC(PWM7),
+ ASPEED_PINCTRL_FUNC(VPI18),
+ ASPEED_PINCTRL_FUNC(VPI24),
+ ASPEED_PINCTRL_FUNC(VPI30),
+ ASPEED_PINCTRL_FUNC(BMCINT),
+ ASPEED_PINCTRL_FUNC(FLACK),
+ ASPEED_PINCTRL_FUNC(I2C3),
+ ASPEED_PINCTRL_FUNC(I2C4),
+ ASPEED_PINCTRL_FUNC(ROM8),
+ ASPEED_PINCTRL_FUNC(ROM16),
+ ASPEED_PINCTRL_FUNC(VPO12),
+ ASPEED_PINCTRL_FUNC(VPO24),
+ ASPEED_PINCTRL_FUNC(RGMII1),
+ ASPEED_PINCTRL_FUNC(RMII1),
+};
+
+static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
+ .pins = aspeed_g4_pins,
+ .npins = ARRAY_SIZE(aspeed_g4_pins),
+ .groups = aspeed_g4_groups,
+ .ngroups = ARRAY_SIZE(aspeed_g4_groups),
+ .functions = aspeed_g4_functions,
+ .nfunctions = ARRAY_SIZE(aspeed_g4_functions),
+};
+
+static struct pinmux_ops aspeed_g4_pinmux_ops = {
+ .get_functions_count = aspeed_pinmux_get_fn_count,
+ .get_function_name = aspeed_pinmux_get_fn_name,
+ .get_function_groups = aspeed_pinmux_get_fn_groups,
+ .set_mux = aspeed_pinmux_set_mux,
+ .gpio_request_enable = aspeed_gpio_request_enable,
+ .strict = true,
+};
+
+static struct pinctrl_ops aspeed_g4_pinctrl_ops = {
+ .get_groups_count = aspeed_pinctrl_get_groups_count,
+ .get_group_name = aspeed_pinctrl_get_group_name,
+ .get_group_pins = aspeed_pinctrl_get_group_pins,
+ .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
+ .name = "aspeed-g4-pinctrl",
+ .pins = aspeed_g4_pins,
+ .npins = ARRAY_SIZE(aspeed_g4_pins),
+ .pctlops = &aspeed_g4_pinctrl_ops,
+ .pmxops = &aspeed_g4_pinmux_ops,
+};
+
+static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++)
+ aspeed_g4_pins[i].number = i;
+
+ return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc,
+ &aspeed_g4_pinctrl_data);
+}
+
+static const struct of_device_id aspeed_g4_pinctrl_of_match[] = {
+ { .compatible = "aspeed,g4-pinctrl", },
+ { },
+};
+
+static struct platform_driver aspeed_g4_pinctrl_driver = {
+ .probe = aspeed_g4_pinctrl_probe,
+ .driver = {
+ .name = "aspeed-g4-pinctrl",
+ .of_match_table = aspeed_g4_pinctrl_of_match,
+ },
+};
+
+static int aspeed_g4_pinctrl_init(void)
+{
+ return platform_driver_register(&aspeed_g4_pinctrl_driver);
+}
+
+arch_initcall(aspeed_g4_pinctrl_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (2 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
` (7 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
A small subset of pins and functions are exposed. The selection of pins
and functions is driven by the development of OpenBMC[1] on the
AST2500 SoC, particularly around booting the IBM Witherspoon platform.
[1] https://github.com/openbmc/docs
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/mach-aspeed/Kconfig | 1 +
drivers/pinctrl/aspeed/Kconfig | 8 +
drivers/pinctrl/aspeed/Makefile | 1 +
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 561 +++++++++++++++++++++++++++++
4 files changed, 571 insertions(+)
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index 2589b90b0a7b..25a0ae01429e 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -25,6 +25,7 @@ config MACH_ASPEED_G5
bool "Aspeed SoC 5th Generation"
depends on ARCH_MULTI_V6
select CPU_V6
+ select PINCTRL_ASPEED_G5
help
Say yes if you intend to run on an Aspeed ast2500 or similar
fifth generation Aspeed BMCs.
diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
index 480a206c69f1..ee45a965bc68 100644
--- a/drivers/pinctrl/aspeed/Kconfig
+++ b/drivers/pinctrl/aspeed/Kconfig
@@ -14,3 +14,11 @@ config PINCTRL_ASPEED_G4
help
Say Y here to enable pin controller support for Aspeed's 4th
generation AST SoCs. GPIO is provided by a separate GPIO driver.
+
+config PINCTRL_ASPEED_G5
+ bool "Aspeed G5 SoC pin control"
+ depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
+ select PINCTRL_ASPEED
+ help
+ Say Y here to enable pin controller support for Aspeed's 5th
+ generation AST SoCs. GPIO is provided by a separate GPIO driver.
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
index 253bddd1fc2d..0f4b8760f936 100644
--- a/drivers/pinctrl/aspeed/Makefile
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
+obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
new file mode 100644
index 000000000000..737a33b05ea2
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-aspeed.h"
+
+#define ASPEED_G5_NR_PINS 228
+
+#define COND1 SIG_DESC_BIT(SCU90, 6, 0)
+#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
+
+#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
+
+#define C14 4
+SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
+MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
+
+FUNC_GROUP_DECL(TIMER5, C14);
+
+#define A13 5
+SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
+SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
+MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
+
+FUNC_GROUP_DECL(TIMER6, A13);
+
+FUNC_GROUP_DECL(I2C9, C14, A13);
+
+#define SD1_DESC SIG_DESC_SET(SCU90, 0)
+
+#define C12 16
+#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
+SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
+MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
+
+#define A12 17
+SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
+MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
+
+FUNC_GROUP_DECL(I2C10, C12, A12);
+
+#define B12 18
+#define I2C11_DESC SIG_DESC_SET(SCU90, 24)
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
+MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
+
+#define D9 19
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
+MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
+
+FUNC_GROUP_DECL(I2C11, B12, D9);
+
+#define D10 20
+#define I2C12_DESC SIG_DESC_SET(SCU90, 25)
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
+MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
+
+#define E12 21
+SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
+MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
+
+FUNC_GROUP_DECL(I2C12, D10, E12);
+
+#define C11 22
+#define I2C13_DESC SIG_DESC_SET(SCU90, 26)
+SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
+MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
+
+#define B11 23
+SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
+MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
+
+FUNC_GROUP_DECL(I2C13, C11, B11);
+FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
+
+#define SD2_DESC SIG_DESC_SET(SCU90, 1)
+#define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
+#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
+
+#define F19 24
+SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
+MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
+
+#define E21 25
+SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
+SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
+MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
+
+FUNC_GROUP_DECL(GPID0, F19, E21);
+
+#define GPID1_DESC SIG_DESC_SET(SCU8C, 9)
+
+#define D20 26
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID1IN, GPID1, GPID1_DESC);
+SIG_EXPR_DECL(GPID1IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID1IN, GPID1, GPID);
+MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID1IN);
+
+#define D21 27
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID1OUT, GPID1, GPID1_DESC);
+SIG_EXPR_DECL(GPID1OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID1OUT, GPID1, GPID);
+MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID1OUT);
+
+FUNC_GROUP_DECL(GPID1, D20, D21);
+
+#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
+
+#define L3 80
+SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
+SS_PIN_DECL(L3, GPIOK0, SCL5);
+
+#define L4 81
+SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
+SS_PIN_DECL(L4, GPIOK1, SDA5);
+
+FUNC_GROUP_DECL(I2C5, L3, L4);
+
+#define I2C6_DESC SIG_DESC_SET(SCU90, 19)
+
+#define L1 82
+SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
+SS_PIN_DECL(L1, GPIOK2, SCL6);
+
+#define N2 83
+SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
+SS_PIN_DECL(N2, GPIOK3, SDA6);
+
+FUNC_GROUP_DECL(I2C6, L1, N2);
+
+#define I2C7_DESC SIG_DESC_SET(SCU90, 20)
+
+#define N1 84
+SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
+SS_PIN_DECL(N1, GPIOK4, SCL7);
+
+#define P1 85
+SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
+SS_PIN_DECL(P1, GPIOK5, SDA7);
+
+FUNC_GROUP_DECL(I2C7, N1, P1);
+
+#define I2C8_DESC SIG_DESC_SET(SCU90, 21)
+
+#define P2 86
+SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
+SS_PIN_DECL(P2, GPIOK6, SCL8);
+
+#define R1 87
+SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
+SS_PIN_DECL(R1, GPIOK7, SDA8);
+
+FUNC_GROUP_DECL(I2C8, P2, R1);
+
+#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
+#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
+#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
+#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
+
+#define V2 104
+#define V2_DESC SIG_DESC_SET(SCU88, 0)
+SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
+MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
+FUNC_GROUP_DECL(PWM0, V2);
+
+#define W2 105
+#define W2_DESC SIG_DESC_SET(SCU88, 1)
+SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
+MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
+FUNC_GROUP_DECL(PWM1, W2);
+
+#define V3 106
+#define V3_DESC SIG_DESC_SET(SCU88, 2)
+SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
+SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
+MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
+FUNC_GROUP_DECL(PWM2, V3);
+
+#define U3 107
+#define U3_DESC SIG_DESC_SET(SCU88, 3)
+SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
+SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
+MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
+FUNC_GROUP_DECL(PWM3, U3);
+
+#define W3 108
+#define W3_DESC SIG_DESC_SET(SCU88, 4)
+SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
+SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
+MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
+FUNC_GROUP_DECL(PWM4, W3);
+
+#define AA3 109
+#define AA3_DESC SIG_DESC_SET(SCU88, 5)
+SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
+SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
+SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
+SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
+MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
+FUNC_GROUP_DECL(PWM5, AA3);
+
+#define Y3 110
+#define Y3_DESC SIG_DESC_SET(SCU88, 6)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
+MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
+FUNC_GROUP_DECL(PWM6, Y3);
+
+#define T4 111
+#define T4_DESC SIG_DESC_SET(SCU88, 7)
+SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
+MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
+FUNC_GROUP_DECL(PWM7, T4);
+
+#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
+
+#define A11 128
+SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
+SS_PIN_DECL(A11, GPIOQ0, SCL3);
+
+#define A10 129
+SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
+SS_PIN_DECL(A10, GPIOQ1, SDA3);
+
+FUNC_GROUP_DECL(I2C3, A11, A10);
+
+#define I2C4_DESC SIG_DESC_SET(SCU90, 17)
+
+#define A9 130
+SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
+SS_PIN_DECL(A9, GPIOQ2, SCL4);
+
+#define B9 131
+SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
+SS_PIN_DECL(B9, GPIOQ3, SDA4);
+
+FUNC_GROUP_DECL(I2C4, A9, B9);
+
+#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
+
+#define N21 132
+SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
+SS_PIN_DECL(N21, GPIOQ4, SCL14);
+
+#define N22 133
+SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
+SS_PIN_DECL(N22, GPIOQ5, SDA14);
+
+FUNC_GROUP_DECL(I2C14, N21, N22);
+
+/* RGMII1/RMII1 */
+
+#define MAC1_RMII { HW_STRAP1, BIT(6), 0, 0 }
+
+#define B5 152
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, MAC1_RMII,
+ SIG_DESC_SET(SCU48, 29));
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
+MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
+ SIG_EXPR_LIST_PTR(RGMII1TXCK));
+
+#define E9 153
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
+MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
+ SIG_EXPR_LIST_PTR(RGMII1TXCTL));
+
+#define F9 154
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
+MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
+ SIG_EXPR_LIST_PTR(RGMII1TXD0));
+
+#define A5 155
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
+MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
+ SIG_EXPR_LIST_PTR(RGMII1TXD1));
+
+#define E7 156
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
+MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
+ SIG_EXPR_LIST_PTR(RGMII1TXD2));
+
+#define D7 157
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
+MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
+ SIG_EXPR_LIST_PTR(RGMII1TXD3));
+
+#define B4 164
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
+MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
+ SIG_EXPR_LIST_PTR(RGMII1RXCK));
+
+#define A4 165
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
+MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
+ SIG_EXPR_LIST_PTR(RGMII1RXCTL));
+
+#define A3 166
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
+MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
+ SIG_EXPR_LIST_PTR(RGMII1RXD0));
+
+#define D6 167
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
+MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
+ SIG_EXPR_LIST_PTR(RGMII1RXD1));
+
+#define C5 168
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
+MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
+ SIG_EXPR_LIST_PTR(RGMII1RXD2));
+
+#define C4 169
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
+SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, MAC1_RMII);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
+MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
+ SIG_EXPR_LIST_PTR(RGMII1RXD3));
+
+FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
+FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
+
+static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
+ ASPEED_PINCTRL_PIN(C14),
+ ASPEED_PINCTRL_PIN(A13),
+ ASPEED_PINCTRL_PIN(C12),
+ ASPEED_PINCTRL_PIN(A12),
+ ASPEED_PINCTRL_PIN(B12),
+ ASPEED_PINCTRL_PIN(D9),
+ ASPEED_PINCTRL_PIN(D10),
+ ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(C11),
+ ASPEED_PINCTRL_PIN(B11),
+ ASPEED_PINCTRL_PIN(F19),
+ ASPEED_PINCTRL_PIN(E21),
+ ASPEED_PINCTRL_PIN(D20),
+ ASPEED_PINCTRL_PIN(D21),
+ ASPEED_PINCTRL_PIN(L3),
+ ASPEED_PINCTRL_PIN(L4),
+ ASPEED_PINCTRL_PIN(L1),
+ ASPEED_PINCTRL_PIN(N2),
+ ASPEED_PINCTRL_PIN(N1),
+ ASPEED_PINCTRL_PIN(P1),
+ ASPEED_PINCTRL_PIN(P2),
+ ASPEED_PINCTRL_PIN(R1),
+ ASPEED_PINCTRL_PIN(V2),
+ ASPEED_PINCTRL_PIN(W2),
+ ASPEED_PINCTRL_PIN(V3),
+ ASPEED_PINCTRL_PIN(U3),
+ ASPEED_PINCTRL_PIN(W3),
+ ASPEED_PINCTRL_PIN(AA3),
+ ASPEED_PINCTRL_PIN(Y3),
+ ASPEED_PINCTRL_PIN(T4),
+ ASPEED_PINCTRL_PIN(A11),
+ ASPEED_PINCTRL_PIN(A10),
+ ASPEED_PINCTRL_PIN(A9),
+ ASPEED_PINCTRL_PIN(B9),
+ ASPEED_PINCTRL_PIN(N21),
+ ASPEED_PINCTRL_PIN(N22),
+ ASPEED_PINCTRL_PIN(D10),
+ ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(B4),
+ ASPEED_PINCTRL_PIN(A4),
+ ASPEED_PINCTRL_PIN(A3),
+ ASPEED_PINCTRL_PIN(D6),
+ ASPEED_PINCTRL_PIN(C5),
+ ASPEED_PINCTRL_PIN(C4),
+ ASPEED_PINCTRL_PIN(B5),
+ ASPEED_PINCTRL_PIN(E9),
+ ASPEED_PINCTRL_PIN(F9),
+ ASPEED_PINCTRL_PIN(A5),
+ ASPEED_PINCTRL_PIN(E7),
+ ASPEED_PINCTRL_PIN(D7),
+};
+
+static const struct aspeed_pin_group aspeed_g5_groups[] = {
+ ASPEED_PINCTRL_GROUP(I2C9),
+ ASPEED_PINCTRL_GROUP(I2C10),
+ ASPEED_PINCTRL_GROUP(I2C11),
+ ASPEED_PINCTRL_GROUP(I2C12),
+ ASPEED_PINCTRL_GROUP(I2C13),
+ ASPEED_PINCTRL_GROUP(SD1),
+ ASPEED_PINCTRL_GROUP(GPID0),
+ ASPEED_PINCTRL_GROUP(GPID1),
+ ASPEED_PINCTRL_GROUP(I2C5),
+ ASPEED_PINCTRL_GROUP(I2C6),
+ ASPEED_PINCTRL_GROUP(I2C7),
+ ASPEED_PINCTRL_GROUP(I2C8),
+ ASPEED_PINCTRL_GROUP(PWM0),
+ ASPEED_PINCTRL_GROUP(PWM1),
+ ASPEED_PINCTRL_GROUP(PWM2),
+ ASPEED_PINCTRL_GROUP(PWM3),
+ ASPEED_PINCTRL_GROUP(PWM4),
+ ASPEED_PINCTRL_GROUP(PWM5),
+ ASPEED_PINCTRL_GROUP(PWM6),
+ ASPEED_PINCTRL_GROUP(PWM7),
+ ASPEED_PINCTRL_GROUP(I2C3),
+ ASPEED_PINCTRL_GROUP(I2C4),
+ ASPEED_PINCTRL_GROUP(I2C14),
+ ASPEED_PINCTRL_GROUP(RMII1),
+ ASPEED_PINCTRL_GROUP(RGMII1),
+};
+
+static const struct aspeed_pin_function aspeed_g5_functions[] = {
+ ASPEED_PINCTRL_FUNC(I2C9),
+ ASPEED_PINCTRL_FUNC(I2C10),
+ ASPEED_PINCTRL_FUNC(I2C11),
+ ASPEED_PINCTRL_FUNC(I2C12),
+ ASPEED_PINCTRL_FUNC(I2C13),
+ ASPEED_PINCTRL_FUNC(SD1),
+ ASPEED_PINCTRL_FUNC(GPID0),
+ ASPEED_PINCTRL_FUNC(GPID1),
+ ASPEED_PINCTRL_FUNC(I2C5),
+ ASPEED_PINCTRL_FUNC(I2C6),
+ ASPEED_PINCTRL_FUNC(I2C7),
+ ASPEED_PINCTRL_FUNC(I2C8),
+ ASPEED_PINCTRL_FUNC(PWM0),
+ ASPEED_PINCTRL_FUNC(PWM1),
+ ASPEED_PINCTRL_FUNC(PWM2),
+ ASPEED_PINCTRL_FUNC(PWM3),
+ ASPEED_PINCTRL_FUNC(PWM4),
+ ASPEED_PINCTRL_FUNC(PWM5),
+ ASPEED_PINCTRL_FUNC(PWM6),
+ ASPEED_PINCTRL_FUNC(PWM7),
+ ASPEED_PINCTRL_FUNC(I2C3),
+ ASPEED_PINCTRL_FUNC(I2C4),
+ ASPEED_PINCTRL_FUNC(I2C14),
+ ASPEED_PINCTRL_FUNC(RMII1),
+ ASPEED_PINCTRL_FUNC(RGMII1),
+};
+
+static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
+ .pins = aspeed_g5_pins,
+ .npins = ARRAY_SIZE(aspeed_g5_pins),
+ .groups = aspeed_g5_groups,
+ .ngroups = ARRAY_SIZE(aspeed_g5_groups),
+ .functions = aspeed_g5_functions,
+ .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
+};
+
+static struct pinmux_ops aspeed_g5_pinmux_ops = {
+ .get_functions_count = aspeed_pinmux_get_fn_count,
+ .get_function_name = aspeed_pinmux_get_fn_name,
+ .get_function_groups = aspeed_pinmux_get_fn_groups,
+ .set_mux = aspeed_pinmux_set_mux,
+ .gpio_request_enable = aspeed_gpio_request_enable,
+ .strict = true,
+};
+
+static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
+ .get_groups_count = aspeed_pinctrl_get_groups_count,
+ .get_group_name = aspeed_pinctrl_get_group_name,
+ .get_group_pins = aspeed_pinctrl_get_group_pins,
+ .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
+ .name = "aspeed-g5-pinctrl",
+ .pins = aspeed_g5_pins,
+ .npins = ARRAY_SIZE(aspeed_g5_pins),
+ .pctlops = &aspeed_g5_pinctrl_ops,
+ .pmxops = &aspeed_g5_pinmux_ops,
+};
+
+static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
+ aspeed_g5_pins[i].number = i;
+
+ return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
+ &aspeed_g5_pinctrl_data);
+}
+
+static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
+ { .compatible = "aspeed,g5-pinctrl", },
+ { },
+};
+
+static struct platform_driver aspeed_g5_pinctrl_driver = {
+ .probe = aspeed_g5_pinctrl_probe,
+ .driver = {
+ .name = "aspeed-g5-pinctrl",
+ .of_match_table = aspeed_g5_pinctrl_of_match,
+ },
+};
+
+static int aspeed_g5_pinctrl_init(void)
+{
+ return platform_driver_register(&aspeed_g5_pinctrl_driver);
+}
+
+arch_initcall(aspeed_g5_pinctrl_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (3 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 19:06 ` Rob Herring
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
` (6 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
.../devicetree/bindings/gpio/gpio-aspeed.txt | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
new file mode 100644
index 000000000000..1954b288cd49
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
@@ -0,0 +1,42 @@
+Aspeed GPIO controller Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- #gpio-cells : Should be two
+ - First cell is the GPIO line number
+ - Second cell is used to specify optional
+ parameters (unused)
+
+- compatible : Either "aspeed,ast2400-gpio" or "aspeed,ast2500-gpio"
+
+- reg : Address and length of the register set for the device
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt specifier (see interrupt bindings for
+ details)
+
+Optional properties:
+- interrupt-controller : Marks the device node as an interrupt controller.
+- interrupt-parent : The parent interrupt controller, optional if inherited
+- #interrupt-cells : Should be 2. The first cell is the GPIO number.
+ The second cell bits[3:0] is used to specify trigger
+ type and level flags:
+ 1 = low-to-high edge triggered.
+ 2 = high-to-low edge triggered.
+ 4 = active high level-sensitive.
+ 8 = active low level-sensitive.
+
+The gpio and interrupt properties are further described in their respective
+bindings documentation:
+
+- Documentation/devicetree/bindings/gpio/gpio.txt
+- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+ Example:
+ gpio at 1e780000 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2400-gpio"
+ gpio-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+ reg = <0x1e780000 0x1000>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/12] gpio: Add Aspeed driver
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (4 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-21 20:12 ` Paul Gortmaker
2016-08-11 9:20 ` Linus Walleij
2016-07-20 5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
` (5 subsequent siblings)
11 siblings, 2 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
From: Joel Stanley <joel@jms.id.au>
The Aspeed SoCs contain GPIOs grouped by letter, where each letter group
contains 8 pins. The GPIO letter groups are then banked in sets of four
in the register layout.
The implementation exposes multiple banks through the one driver, and
requests and releases pins via the pinctrl subsystem. The hardware
supports generation of interrupts with per-pin triggers, and exposes this
capability through an irqchip and devicetree.
A number of supported features are not yet implemented: Configuration of
interrupt direction (ARM or LPC), debouncing, and provides WDT reset
tolerance for output ports.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/mach-aspeed/Kconfig | 4 +
drivers/gpio/Kconfig | 8 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-aspeed.c | 456 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 468 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpio/gpio-aspeed.c
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index 25a0ae01429e..a52de9d3adfb 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
select ASPEED_WATCHDOG
select MOXART_TIMER
select PINCTRL
+ select GPIOLIB
+ select GPIO_ASPEED
+ select GPIO_SYSFS
+
help
Say Y here if you want to run your kernel on an ASpeed BMC SoC.
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 536112fd2466..2c21b5db09cd 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -137,6 +137,13 @@ config GPIO_ATH79
Select this option to enable GPIO driver for
Atheros AR71XX/AR724X/AR913X SoC devices.
+config GPIO_ASPEED
+ bool "Aspeed GPIO support"
+ depends on (ARCH_ASPEED || COMPILE_TEST) && OF
+ select GENERIC_IRQ_CHIP
+ help
+ Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers.
+
config GPIO_BCM_KONA
bool "Broadcom Kona GPIO"
depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
@@ -1072,7 +1079,6 @@ config GPIO_SODAVILLE
select GENERIC_IRQ_CHIP
help
Say Y here to support Intel Sodaville GPIO.
-
endmenu
menu "SPI GPIO expanders"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 991598ea3fba..a2b18beb8af5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
+obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
new file mode 100644
index 000000000000..7885adc1332a
--- /dev/null
+++ b/drivers/gpio/gpio-aspeed.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright 2015 IBM Corp.
+ *
+ * Joel Stanley <joel@jms.id.au>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/gpio/driver.h>
+#include <linux/pinctrl/consumer.h>
+
+struct aspeed_gpio {
+ struct gpio_chip chip;
+ spinlock_t lock;
+ void __iomem *base;
+ int irq;
+ struct irq_chip irq_chip;
+ struct irq_domain *irq_domain;
+};
+
+struct aspeed_gpio_bank {
+ uint16_t val_regs;
+ uint16_t irq_regs;
+ const char names[4];
+};
+
+static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
+ {
+ .val_regs = 0x0000,
+ .irq_regs = 0x0008,
+ .names = { 'A', 'B', 'C', 'D' },
+ },
+ {
+ .val_regs = 0x0020,
+ .irq_regs = 0x0028,
+ .names = { 'E', 'F', 'G', 'H' },
+ },
+ {
+ .val_regs = 0x0070,
+ .irq_regs = 0x0098,
+ .names = { 'I', 'J', 'K', 'L' },
+ },
+ {
+ .val_regs = 0x0078,
+ .irq_regs = 0x00e8,
+ .names = { 'M', 'N', 'O', 'P' },
+ },
+ {
+ .val_regs = 0x0080,
+ .irq_regs = 0x0118,
+ .names = { 'Q', 'R', 'S', 'T' },
+ },
+ {
+ .val_regs = 0x0088,
+ .irq_regs = 0x0148,
+ .names = { 'U', 'V', 'W', 'X' },
+ },
+ /*
+ * A bank exists for { 'Y', 'Z', "AA", "AB" }, but is not implemented.
+ * Only half of GPIOs Y support interrupt configuration, and none of Z,
+ * AA or AB do as they are output only.
+ */
+};
+
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_OFFSET(x) ((x) & 0x1f)
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
+
+#define GPIO_DATA 0x00
+#define GPIO_DIR 0x04
+
+#define GPIO_IRQ_ENABLE 0x00
+#define GPIO_IRQ_TYPE0 0x04
+#define GPIO_IRQ_TYPE1 0x08
+#define GPIO_IRQ_TYPE2 0x0c
+#define GPIO_IRQ_STATUS 0x10
+
+static inline struct aspeed_gpio *to_aspeed_gpio(struct gpio_chip *chip)
+{
+ return container_of(chip, struct aspeed_gpio, chip);
+}
+
+static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
+{
+ unsigned int bank = GPIO_BANK(offset);
+
+ WARN_ON(bank > ARRAY_SIZE(aspeed_gpio_banks));
+ return &aspeed_gpio_banks[bank];
+}
+
+static void *bank_val_reg(struct aspeed_gpio *gpio,
+ const struct aspeed_gpio_bank *bank,
+ unsigned int reg)
+{
+ return gpio->base + bank->val_regs + reg;
+}
+
+static void *bank_irq_reg(struct aspeed_gpio *gpio,
+ const struct aspeed_gpio_bank *bank,
+ unsigned int reg)
+{
+ return gpio->base + bank->irq_regs + reg;
+}
+
+static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_gpio *gpio = to_aspeed_gpio(gc);
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+
+ return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA))
+ & GPIO_BIT(offset));
+}
+
+static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int val)
+{
+ struct aspeed_gpio *gpio = to_aspeed_gpio(gc);
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(bank_val_reg(gpio, bank, GPIO_DATA));
+ if (val)
+ reg |= GPIO_BIT(offset);
+ else
+ reg &= ~GPIO_BIT(offset);
+
+ iowrite32(reg, bank_val_reg(gpio, bank, GPIO_DATA));
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_gpio *gpio = to_aspeed_gpio(gc);
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
+ iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_gpio_dir_out(struct gpio_chip *gc,
+ unsigned int offset, int val)
+{
+ struct aspeed_gpio *gpio = to_aspeed_gpio(gc);
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
+ iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
+ struct aspeed_gpio **gpio,
+ const struct aspeed_gpio_bank **bank,
+ u32 *bit)
+{
+ int offset;
+
+ offset = irqd_to_hwirq(d);
+
+ *gpio = irq_data_get_irq_chip_data(d);
+ *bank = to_bank(offset);
+ *bit = GPIO_BIT(offset);
+
+ return 0;
+}
+
+static void aspeed_gpio_irq_ack(struct irq_data *d)
+{
+ const struct aspeed_gpio_bank *bank;
+ struct aspeed_gpio *gpio;
+ unsigned long flags;
+ void *status_addr;
+ u32 bit;
+ int rc;
+
+ rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
+ if (rc)
+ return;
+
+ status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+ iowrite32(bit, status_addr);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void __aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
+{
+ const struct aspeed_gpio_bank *bank;
+ struct aspeed_gpio *gpio;
+ unsigned long flags;
+ u32 reg, bit;
+ void *addr;
+ int rc;
+
+ rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
+ if (rc)
+ return;
+
+ addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(addr);
+ if (set)
+ reg |= bit;
+ else
+ reg &= bit;
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void aspeed_gpio_irq_mask(struct irq_data *d)
+{
+ __aspeed_gpio_irq_set_mask(d, false);
+}
+
+static void aspeed_gpio_irq_unmask(struct irq_data *d)
+{
+ __aspeed_gpio_irq_set_mask(d, true);
+}
+
+static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 type0, type1, type2, bit, reg;
+ const struct aspeed_gpio_bank *bank;
+ irq_flow_handler_t handler;
+ struct aspeed_gpio *gpio;
+ unsigned long flags;
+ void *addr;
+ int rc;
+
+ rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
+ if (rc)
+ return -EINVAL;
+
+ type0 = type1 = type2 = 0;
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_EDGE_BOTH:
+ type2 |= bit;
+ case IRQ_TYPE_EDGE_RISING:
+ type0 |= bit;
+ case IRQ_TYPE_EDGE_FALLING:
+ handler = handle_edge_irq;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ type0 |= bit;
+ case IRQ_TYPE_LEVEL_LOW:
+ type1 |= bit;
+ handler = handle_level_irq;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type0;
+ iowrite32(reg, addr);
+
+ addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type1;
+ iowrite32(reg, addr);
+
+ addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type2;
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ irq_set_handler_locked(d, handler);
+
+ return 0;
+}
+
+static void aspeed_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct aspeed_gpio *gpio = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int i, p, girq;
+ unsigned long reg;
+
+ chained_irq_enter(chip, desc);
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
+ const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
+
+ reg = ioread32(bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS));
+
+ for_each_set_bit(p, ®, 32) {
+ girq = irq_find_mapping(gpio->irq_domain, i * 32 + p);
+ generic_handle_irq(girq);
+ }
+
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip aspeed_gpio_irqchip = {
+ .name = "aspeed-gpio",
+ .irq_ack = aspeed_gpio_irq_ack,
+ .irq_mask = aspeed_gpio_irq_mask,
+ .irq_unmask = aspeed_gpio_irq_unmask,
+ .irq_set_type = aspeed_gpio_set_type,
+};
+
+static int aspeed_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+ struct aspeed_gpio *gpio = to_aspeed_gpio(chip);
+
+ return irq_find_mapping(gpio->irq_domain, offset);
+}
+
+static void aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
+ struct platform_device *pdev)
+{
+ int i, irq;
+
+ /* request our upstream IRQ */
+ gpio->irq = platform_get_irq(pdev, 0);
+ if (gpio->irq < 0)
+ return;
+
+ /* establish our irq domain to provide IRQs for each extended bank */
+ gpio->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
+ gpio->chip.ngpio, &irq_domain_simple_ops, NULL);
+ if (!gpio->irq_domain)
+ return;
+
+ for (i = 0; i < gpio->chip.ngpio; i++) {
+ irq = irq_create_mapping(gpio->irq_domain, i);
+ irq_set_chip_data(irq, gpio);
+ irq_set_chip_and_handler(irq, &aspeed_gpio_irqchip,
+ handle_simple_irq);
+ irq_set_probe(irq);
+ }
+
+ irq_set_chained_handler_and_data(gpio->irq,
+ aspeed_gpio_irq_handler, gpio);
+}
+
+static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+}
+
+static int __init aspeed_gpio_probe(struct platform_device *pdev)
+{
+ struct aspeed_gpio *gpio;
+ struct resource *res;
+ int rc;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENXIO;
+
+ gpio->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!gpio->base)
+ return -ENOMEM;
+
+ spin_lock_init(&gpio->lock);
+
+ gpio->chip.ngpio = ARRAY_SIZE(aspeed_gpio_banks) * 32;
+
+ gpio->chip.parent = &pdev->dev;
+ gpio->chip.direction_input = aspeed_gpio_dir_in;
+ gpio->chip.direction_output = aspeed_gpio_dir_out;
+ gpio->chip.request = aspeed_gpio_request;
+ gpio->chip.free = aspeed_gpio_free;
+ gpio->chip.get = aspeed_gpio_get;
+ gpio->chip.set = aspeed_gpio_set;
+ gpio->chip.to_irq = aspeed_gpio_to_irq;
+ gpio->chip.label = dev_name(&pdev->dev);
+ gpio->chip.base = -1;
+
+ platform_set_drvdata(pdev, gpio);
+
+ rc = gpiochip_add(&gpio->chip);
+ if (rc < 0)
+ return rc;
+
+ aspeed_gpio_setup_irqs(gpio, pdev);
+
+ return 0;
+}
+
+static int aspeed_gpio_remove(struct platform_device *pdev)
+{
+ struct aspeed_gpio *gpio = platform_get_drvdata(pdev);
+
+ gpiochip_remove(&gpio->chip);
+ return 0;
+}
+
+static const struct of_device_id aspeed_gpio_of_table[] = {
+ { .compatible = "aspeed,ast2400-gpio" },
+ { .compatible = "aspeed,ast2500-gpio" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
+
+static struct platform_driver aspeed_gpio_driver = {
+ .remove = aspeed_gpio_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = aspeed_gpio_of_table,
+ },
+};
+
+module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
+
+MODULE_DESCRIPTION("Aspeed GPIO Driver");
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (5 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 19:09 ` Rob Herring
2016-07-20 5:58 ` [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes Andrew Jeffery
` (4 subsequent siblings)
11 siblings, 1 reply; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
new file mode 100644
index 000000000000..4df798799101
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
@@ -0,0 +1,16 @@
+The Aspeed System Control Unit manages the global behaviour of the SoC,
+configuring elements such as clocks, pinmux, and reset.
+
+Required properties:
+- compatible: One of:
+ "aspeed,g4-scu", "syscon", "simple-mfd"
+ "aspeed,g5-scu", "syscon", "simple-mfd"
+
+- reg: contains the offset and length of the SCU memory region
+
+Example:
+
+syscon: syscon at 1e6e2000 {
+ compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (6 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 09/12] palmetto: Request relevant mux functions in devicetree Andrew Jeffery
` (3 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
The pin controller's child nodes expose the functions currently
implemented in the the g4 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 284 +++++++++++++++++++++++++++++++++++++++
1 file changed, 284 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 22dee5937d5c..a62d1b5b5054 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -54,6 +54,290 @@
clocks = <&clk_clkin>;
};
+ syscon: syscon at 1e6e2000 {
+ compatible = "aspeed,g4-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl at 1e6e2000 {
+ compatible = "aspeed,g4-pinctrl";
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_timer5_default: timer5_default {
+ function = "TIMER5";
+ groups = "TIMER5";
+ };
+
+ pinctrl_timer6_default: timer6_default {
+ function = "TIMER6";
+ groups = "TIMER6";
+ };
+
+ pinctrl_mdio2_default: mdio2_default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
+
+ pinctrl_timer7_default: timer7_default {
+ function = "TIMER7";
+ groups = "TIMER7";
+ };
+
+ pinctrl_timer8_default: timer8_default {
+ function = "TIMER8";
+ groups = "TIMER8";
+ };
+
+ pinctrl_lpcpd_default: lpcpd {
+ function = "LPCPD";
+ groups = "LPCPD";
+ };
+
+ pinctrl_lpcsmi_default: lpcsmi {
+ function = "LPCSMI";
+ groups = "LPCSMI";
+ };
+
+ pinctrl_lpcpme_default: lpcpme {
+ function = "LPCPME";
+ groups = "LPCPME";
+ };
+
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
+
+ pinctrl_ncts3_default: ncts3_default {
+ function = "NCTS3";
+ groups = "NCTS3";
+ };
+
+ pinctrl_ndcd3_default: ndcd3_default {
+ function = "NDCD3";
+ groups = "NDCD3";
+ };
+
+ pinctrl_gpie0_default: gpie0_default {
+ function = "GPIE0";
+ groups = "GPIE0";
+ };
+
+ pinctrl_ncts4_default: ncts4_default {
+ function = "NCTS4";
+ groups = "NCTS4";
+ };
+
+ pinctrl_ndcd4_default: ndcd4_default {
+ function = "NDCD4";
+ groups = "NDCD4";
+ };
+
+ pinctrl_nri4_default: nri4_default {
+ function = "NRI4";
+ groups = "NRI4";
+ };
+
+ pinctrl_txd4_default: txd4_default {
+ function = "TXD4";
+ groups = "TXD4";
+ };
+
+ pinctrl_rxd4_default: rxd4_default {
+ function = "RXD4";
+ groups = "RXD4";
+ };
+
+ pinctrl_flbusy_default: flbusy {
+ function = "FLBUSY";
+ groups = "FLBUSY";
+ };
+
+ pinctrl_flwp_default: flwp {
+ function = "FLWP";
+ groups = "FLWP";
+ };
+
+ pinctrl_sgpmi_default: sgpmi {
+ function = "SGPMI";
+ groups = "SGPMI";
+ };
+
+ pinctrl_vgahs_default: vgahs {
+ function = "VGAHS";
+ groups = "VGAHS";
+ };
+
+ pinctrl_vgavs_default: vgavs {
+ function = "VGAVS";
+ groups = "VGAVS";
+ };
+
+ pinctrl_ddcclk_default: ddcclk {
+ function = "DDCCLK";
+ groups = "DDCCLK";
+ };
+
+ pinctrl_ddcdat_default: ddcdat {
+ function = "DDCDAT";
+ groups = "DDCDAT";
+ };
+
+ pinctrl_ncts1_default: ncts1_default {
+ function = "NCTS1";
+ groups = "NCTS1";
+ };
+
+ pinctrl_ndcd1_default: ndcd1_default {
+ function = "NDCD1";
+ groups = "NDCD1";
+ };
+
+ pinctrl_nri1_default: nri1_default {
+ function = "NRI1";
+ groups = "NRI1";
+ };
+
+ pinctrl_ndtr1_default: ndtr1_default {
+ function = "NDTR1";
+ groups = "NDTR1";
+ };
+
+ pinctrl_nrts1_default: nrts1_default {
+ function = "NRTS1";
+ groups = "NRTS1";
+ };
+
+ pinctrl_txd1_default: txd1_default {
+ function = "TXD1";
+ groups = "TXD1";
+ };
+
+ pinctrl_rxd1_default: rxd1_default {
+ function = "RXD1";
+ groups = "RXD1";
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_bmcint_default: bmcint {
+ function = "BMCINT";
+ groups = "BMCINT";
+ };
+
+ pinctrl_flack_default: flack {
+ function = "FLACK";
+ groups = "FLACK";
+ };
+
+ pinctrl_rom8_default: rom8 {
+ function = "ROM8";
+ groups = "ROM8";
+ };
+
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+ };
+ };
+
clk_apb: clk_apb at 1e6e2008 {
#clock-cells = <0>;
compatible = "aspeed,g4-apb-clock";
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/12] palmetto: Request relevant mux functions in devicetree
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (7 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree Andrew Jeffery
` (2 subsequent siblings)
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
The requested functions are parented by the pinctrl node to provide the
Palmetto's static pin configuration.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index cc5fcf2940bf..d8d05ee4956b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -20,6 +20,34 @@
};
};
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
+ &pinctrl_vgahs_default &pinctrl_vgavs_default
+ &pinctrl_ddcclk_default &pinctrl_ddcdat_default
+ &pinctrl_pwm0_default &pinctrl_pwm1_default
+ &pinctrl_pwm2_default &pinctrl_pwm3_default
+ &pinctrl_pwm4_default &pinctrl_pwm5_default
+ &pinctrl_pwm6_default &pinctrl_pwm7_default
+ &pinctrl_bmcint_default &pinctrl_flack_default
+ &pinctrl_rom8_default>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncts1_default &pinctrl_ndcd1_default
+ &pinctrl_nri1_default &pinctrl_ndtr1_default
+ &pinctrl_nrts1_default &pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncts4_default &pinctrl_ndcd4_default
+ &pinctrl_nri4_default &pinctrl_txd4_default
+ &pinctrl_rxd4_default>;
+};
+
&uart5 {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (8 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 09/12] palmetto: Request relevant mux functions in devicetree Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20 5:58 ` [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree Andrew Jeffery
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index a62d1b5b5054..2b7da0fdfbd9 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -356,6 +356,15 @@
reg = <0x1e720000 0x8000>; // 32K
};
+ gpio: gpio at 1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2400-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ };
+
timer: timer at 1e782000 {
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (9 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree Andrew Jeffery
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
The pin controller's child nodes expose the functions currently
implemented in the g5 pin controller driver.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 134 +++++++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index dd94d9361fda..1b1910e5eaa3 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -44,6 +44,140 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon at 1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl at 1e6e2000 {
+ compatible = "aspeed,g5-pinctrl";
+
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
+
+ pinctrl_gpid1_default: gpid1_default {
+ function = "GPID1";
+ groups = "GPID1";
+ };
+
+ pinctrl_sd1_default: sd1_default {
+ function = "SD1";
+ groups = "SD1";
+ };
+
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c14_default: i2c14_default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
+
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+ };
+ };
+
clk_hpll: clk_hpll at 1e6e2024 {
#clock-cells = <0>;
compatible = "aspeed,g5-hpll-clock";
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
` (10 preceding siblings ...)
2016-07-20 5:58 ` [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes Andrew Jeffery
@ 2016-07-20 5:58 ` Andrew Jeffery
11 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 5:58 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 1b1910e5eaa3..f5ab29bf3e9e 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -210,6 +210,15 @@
reg = <0x1e720000 0x9000>; // 36K
};
+ gpio: gpio at 1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2400-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ };
+
timer: timer at 1e782000 {
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
--
2.7.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
@ 2016-07-20 19:05 ` Rob Herring
2016-07-20 23:13 ` Andrew Jeffery
0 siblings, 1 reply; 28+ messages in thread
From: Rob Herring @ 2016-07-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 03:28:22PM +0930, Andrew Jeffery wrote:
> Outline expectations on the pin controller's relationship with the
> System Control Unit (SCU) IP through syscon, and document the compatible
> strings for 4th and 5th generation Aspeed SoC pin controllers.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> new file mode 100644
> index 000000000000..5aac6a0a2e89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> @@ -0,0 +1,45 @@
> +Aspeed Pin Controllers
> +----------------------
> +
> +The Aspeed SoCs vary in functionality inside a generation but have a common mux
> +device register layout.
> +
> +Required properties:
> +- compatible: should be one of the following:
> + "aspeed,g4-pinctrl";
> + "aspeed,g5-pinctrl"
> +
> +The pin controller node should be a child of a syscon node with the required
> +property:
> +- compatible: "syscon", "simple-mfd"
> +
> +Refer to the the bindings described in
> +Documentation/devicetree/bindings/mfd/syscon.txt
> +
> +Subnode format:
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices.
> +
> +The required properties of child nodes are (as defined in pinctrl-bindings):
> +- function
> +- groups
> +
> +Each function has only one associated pin group. Each group is named by its
> +function.
> +
> +Examples:
> +
> +syscon: scu at 1e6e2000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x1e6e2000 0x1a8>;
> +
> + pinctrl: pinctrl at 1e6e2000 {
> + compatible = "aspeed,g4-pinctrl";
> +
> + pinctrl_i2c3_default: i2c3_default {
> + function = "I2C3";
> + groups = "I2C3";
All these strings need to be documented.
> + };
> + };
> +};
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1209323b7e43..b5f2d3576d3a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1003,6 +1003,7 @@ S: Maintained
> F: arch/arm/mach-aspeed/
> F: arch/arm/boot/dts/aspeed-*
> F: drivers/*/*aspeed*
> +F: Documentation/devicetree/bindings/*/*aspeed*
>
> ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
> M: Nicolas Ferre <nicolas.ferre@atmel.com>
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers
2016-07-20 5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
@ 2016-07-20 19:06 ` Rob Herring
0 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2016-07-20 19:06 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 03:28:26PM +0930, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> .../devicetree/bindings/gpio/gpio-aspeed.txt | 42 ++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units
2016-07-20 5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
@ 2016-07-20 19:09 ` Rob Herring
2016-07-21 1:04 ` Andrew Jeffery
0 siblings, 1 reply; 28+ messages in thread
From: Rob Herring @ 2016-07-20 19:09 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 03:28:28PM +0930, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
> new file mode 100644
> index 000000000000..4df798799101
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
> @@ -0,0 +1,16 @@
> +The Aspeed System Control Unit manages the global behaviour of the SoC,
> +configuring elements such as clocks, pinmux, and reset.
> +
> +Required properties:
> +- compatible: One of:
> + "aspeed,g4-scu", "syscon", "simple-mfd"
> + "aspeed,g5-scu", "syscon", "simple-mfd"
These (and the pinctrl probably) really need SoC specific compatible
strings. You can keep these as fallbacks though. These are the parts of
SoCs that really vary chip to chip.
Rob
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers
2016-07-20 19:05 ` Rob Herring
@ 2016-07-20 23:13 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-20 23:13 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2016-07-20 at 14:05 -0500, Rob Herring wrote:
> On Wed, Jul 20, 2016 at 03:28:22PM +0930, Andrew Jeffery wrote:
> >
> > Outline expectations on the pin controller's relationship with the
> > System Control Unit (SCU) IP through syscon, and document the compatible
> > strings for 4th and 5th generation Aspeed SoC pin controllers.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > ?.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 45 ++++++++++++++++++++++
> > ?MAINTAINERS????????????????????????????????????????|??1 +
> > ?2 files changed, 46 insertions(+)
> > ?create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > new file mode 100644
> > index 000000000000..5aac6a0a2e89
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > @@ -0,0 +1,45 @@
> > +Aspeed Pin Controllers
> > +----------------------
> > +
> > +The Aspeed SoCs vary in functionality inside a generation but have a common mux
> > +device register layout.
> > +
> > +Required properties:
> > +- compatible: should be one of the following:
> > + "aspeed,g4-pinctrl";
> > + "aspeed,g5-pinctrl"
> > +
> > +The pin controller node should be a child of a syscon node with the required
> > +property:
> > +- compatible: "syscon", "simple-mfd"
> > +
> > +Refer to the the bindings described in
> > +Documentation/devicetree/bindings/mfd/syscon.txt
> > +
> > +Subnode format:
> > +
> > +Please refer to pinctrl-bindings.txt in this directory for details of the
> > +common pinctrl bindings used by client devices.
> > +
> > +The required properties of child nodes are (as defined in pinctrl-bindings):
> > +- function
> > +- groups
> > +
> > +Each function has only one associated pin group. Each group is named by its
> > +function.
> > +
> > +Examples:
> > +
> > +syscon: scu at 1e6e2000 {
> > + compatible = "syscon", "simple-mfd";
> > + reg = <0x1e6e2000 0x1a8>;
> > +
> > + pinctrl: pinctrl at 1e6e2000 {
> > + compatible = "aspeed,g4-pinctrl";
> > +
> > + pinctrl_i2c3_default: i2c3_default {
> > + function = "I2C3";
> > + groups = "I2C3";
> All these strings need to be documented.
Right! Will do.
Cheers,
Andrew
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* [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units
2016-07-20 19:09 ` Rob Herring
@ 2016-07-21 1:04 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-21 1:04 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2016-07-20 at 14:09 -0500, Rob Herring wrote:
> On Wed, Jul 20, 2016 at 03:28:28PM +0930, Andrew Jeffery wrote:
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > ?Documentation/devicetree/bindings/mfd/aspeed-scu.txt | 16 ++++++++++++++++
> > ?1 file changed, 16 insertions(+)
> > ?create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-scu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
> > new file mode 100644
> > index 000000000000..4df798799101
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt
> > @@ -0,0 +1,16 @@
> > +The Aspeed System Control Unit manages the global behaviour of the SoC,
> > +configuring elements such as clocks, pinmux, and reset.
> > +
> > +Required properties:
> > +- compatible: One of:
> > + "aspeed,g4-scu", "syscon", "simple-mfd"
> > + "aspeed,g5-scu", "syscon", "simple-mfd"
> These (and the pinctrl probably) really need SoC specific compatible?
> strings. You can keep these as fallbacks though. These are the parts of?
> SoCs that really vary chip to chip.
I'll add the SoC-specific compatible strings.
Cheers,
Andrew
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 06/12] gpio: Add Aspeed driver
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
@ 2016-07-21 20:12 ` Paul Gortmaker
2016-07-22 0:49 ` Andrew Jeffery
2016-08-11 9:20 ` Linus Walleij
1 sibling, 1 reply; 28+ messages in thread
From: Paul Gortmaker @ 2016-07-21 20:12 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 1:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> The Aspeed SoCs contain GPIOs grouped by letter, where each letter group
> contains 8 pins. The GPIO letter groups are then banked in sets of four
> in the register layout.
>
> The implementation exposes multiple banks through the one driver, and
> requests and releases pins via the pinctrl subsystem. The hardware
> supports generation of interrupts with per-pin triggers, and exposes this
> capability through an irqchip and devicetree.
>
> A number of supported features are not yet implemented: Configuration of
> interrupt direction (ARM or LPC), debouncing, and provides WDT reset
> tolerance for output ports.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> arch/arm/mach-aspeed/Kconfig | 4 +
> drivers/gpio/Kconfig | 8 +-
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-aspeed.c | 456 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 468 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpio/gpio-aspeed.c
>
> diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
> index 25a0ae01429e..a52de9d3adfb 100644
> --- a/arch/arm/mach-aspeed/Kconfig
> +++ b/arch/arm/mach-aspeed/Kconfig
> @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
> select ASPEED_WATCHDOG
> select MOXART_TIMER
> select PINCTRL
> + select GPIOLIB
> + select GPIO_ASPEED
> + select GPIO_SYSFS
> +
> help
> Say Y here if you want to run your kernel on an ASpeed BMC SoC.
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 536112fd2466..2c21b5db09cd 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -137,6 +137,13 @@ config GPIO_ATH79
> Select this option to enable GPIO driver for
> Atheros AR71XX/AR724X/AR913X SoC devices.
>
> +config GPIO_ASPEED
> + bool "Aspeed GPIO support"
Since this is a bool Kconfig...
> + depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> + select GENERIC_IRQ_CHIP
> + help
> + Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers.
> +
[...]
> diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
> new file mode 100644
> index 000000000000..7885adc1332a
> --- /dev/null
> +++ b/drivers/gpio/gpio-aspeed.c
> @@ -0,0 +1,456 @@
> +/*
> + * Copyright 2015 IBM Corp
> + *
> + * Joel Stanley <joel@jms.id.au>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/module.h>
...can you please get rid of module.h and all the MODULE_<xyz>
stuff and use the built in registration? Alternatively change it to
a tristate if there is a valid use case for it to be modular.
Thanks.
Paul.
--
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/pinctrl/consumer.h>
> +
> +struct aspeed_gpio {
> + struct gpio_chip chip;
> + spinlock_t lock;
> + void __iomem *base;
> + int irq;
> + struct irq_chip irq_chip;
> + struct irq_domain *irq_domain;
> +};
> +
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 06/12] gpio: Add Aspeed driver
2016-07-21 20:12 ` Paul Gortmaker
@ 2016-07-22 0:49 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-07-22 0:49 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2016-07-21 at 16:12 -0400, Paul Gortmaker wrote:
> On Wed, Jul 20, 2016 at 1:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > From: Joel Stanley <joel@jms.id.au>
> >
> > The Aspeed SoCs contain GPIOs grouped by letter, where each letter group
> > contains 8 pins. The GPIO letter groups are then banked in sets of four
> > in the register layout.
> >
> > The implementation exposes multiple banks through the one driver, and
> > requests and releases pins via the pinctrl subsystem. The hardware
> > supports generation of interrupts with per-pin triggers, and exposes this
> > capability through an irqchip and devicetree.
> >
> > A number of supported features are not yet implemented: Configuration of
> > interrupt direction (ARM or LPC), debouncing, and provides WDT reset
> > tolerance for output ports.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > Signed-off-by: Alistair Popple <alistair@popple.id.au>
> > Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > ?arch/arm/mach-aspeed/Kconfig |???4 +
> > ?drivers/gpio/Kconfig?????????|???8 +-
> > ?drivers/gpio/Makefile????????|???1 +
> > ?drivers/gpio/gpio-aspeed.c???| 456 +++++++++++++++++++++++++++++++++++++++++++
> > ?4 files changed, 468 insertions(+), 1 deletion(-)
> > ?create mode 100644 drivers/gpio/gpio-aspeed.c
> >
> > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
> > index 25a0ae01429e..a52de9d3adfb 100644
> > --- a/arch/arm/mach-aspeed/Kconfig
> > +++ b/arch/arm/mach-aspeed/Kconfig
> > @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
> > ????????select ASPEED_WATCHDOG
> > ????????select MOXART_TIMER
> > ????????select PINCTRL
> > +???????select GPIOLIB
> > +???????select GPIO_ASPEED
> > +???????select GPIO_SYSFS
> > +
> > ????????help
> > ??????????Say Y here if you want to run your kernel on an ASpeed BMC SoC.
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 536112fd2466..2c21b5db09cd 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -137,6 +137,13 @@ config GPIO_ATH79
> > ??????????Select this option to enable GPIO driver for
> > ??????????Atheros AR71XX/AR724X/AR913X SoC devices.
> >
> > +config GPIO_ASPEED
> > +???????bool "Aspeed GPIO support"
> Since this is a bool Kconfig...
>
> >
> > +???????depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> > +???????select GENERIC_IRQ_CHIP
> > +???????help
> > +?????????Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers.
> > +
> [...]
>
> ?> diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
> >
> > new file mode 100644
> > index 000000000000..7885adc1332a
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-aspeed.c
> > @@ -0,0 +1,456 @@
> > +/*
> > + * Copyright 2015 IBM Corp
> > + *
> > + * Joel Stanley <joel@jms.id.au>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License
> > + * as published by the Free Software Foundation; either version
> > + * 2 of the License, or (at your option) any later version.
> > + */
> > +
> > +#include
> ...can you please get rid of module.h and all the MODULE_
> stuff and use the built in registration????Alternatively change it to
> a tristate if there is a valid use case for it to be modular.
>
I'll change it to tristate; I don't see a reason to require it be built
in.
Cheers,
Andrew
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* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
@ 2016-07-22 6:29 ` Joel Stanley
2016-08-11 8:41 ` Linus Walleij
1 sibling, 0 replies; 28+ messages in thread
From: Joel Stanley @ 2016-07-22 6:29 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 3:28 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The Aspeed SoCs provide typically more than 200 pins for GPIO and other
> functions. The signal enabled on a pin is determined on a priority
> basis, where a given pin can provide a number of different signal types.
>
> In addition to the priority levels, the Aspeed pin controllers describe
> the signal active on a pin by compound logical expressions involving
> multiple operators, registers and bits. Some difficulty arises as a
> pin's function bit masks for each priority level are frequently not the
> same (i.e. we cannot just flip a bit to change from a high to low
> priority signal), or even in the same register(s). Some configuration
> bits affect multiple pins, while in other cases the signals for a bus
> must each be enabled individually.
>
> Together, these features give rise to some complexity in the
> implementation. A more complete description of the complexities is
> provided in the associated header file in an attempt to justify the
> approach.
>
> Note that the patch doesn't implement pinctrl/pinmux/pinconf for any
> particular SoC, just adds the framework for defining mux configurations
> for any available functions.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> MAINTAINERS | 1 +
> arch/arm/mach-aspeed/Kconfig | 1 +
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/aspeed/Kconfig | 8 +
> drivers/pinctrl/aspeed/Makefile | 3 +
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 373 +++++++++++++++++++++
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 562 ++++++++++++++++++++++++++++++++
> 8 files changed, 950 insertions(+)
> create mode 100644 drivers/pinctrl/aspeed/Kconfig
> create mode 100644 drivers/pinctrl/aspeed/Makefile
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.c
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed.h
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
2016-07-22 6:29 ` Joel Stanley
@ 2016-08-11 8:41 ` Linus Walleij
2016-08-12 0:33 ` Andrew Jeffery
1 sibling, 1 reply; 28+ messages in thread
From: Linus Walleij @ 2016-08-11 8:41 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> --- a/arch/arm/mach-aspeed/Kconfig
> +++ b/arch/arm/mach-aspeed/Kconfig
> @@ -5,6 +5,7 @@ menuconfig ARCH_ASPEED
> select WATCHDOG
> select ASPEED_WATCHDOG
> select MOXART_TIMER
> + select PINCTRL
> help
> Say Y here if you want to run your kernel on an ASpeed BMC SoC.
This needs to be a separate patch sent to the ARM SoC tree.
I don't like to merge patches to other subsystems if it can be
avoided.
> +static inline void aspeed_sig_desc_print_val(
> + const struct aspeed_sig_desc *desc, bool enable, u32 rv)
> +{
> +#if defined(CONFIG_DEBUG_PINCTRL)
> + pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
> + desc->mask, enable ? desc->enable : desc->disable,
> + (rv & desc->mask) >> __ffs(desc->mask), rv);
> +#endif
> +}
You can just use pr_debug(). CONFIG_DEBUG_PINCTRL enables
DEBUG_KERNEL which activates debug prints so this is a truism.
> +static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> + bool enabled, struct regmap *map)
> +static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
> + bool enabled, struct regmap *map)
These need kerneldoc too, they are kind of hard to understand.
> +static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
> +{
> + if (!exprs)
> + return false;
> +
> + while (*exprs) {
> + if (strncmp((*exprs)->signal, "GPIO", 4) == 0)
> + return true;
This looks a bit fragile and hard to debug. Do you have some better
idea of how to do this but not resort to string comparison?
Apart from that it looks pretty alright, complex but such is life
with complex hardware.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 06/12] gpio: Add Aspeed driver
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
2016-07-21 20:12 ` Paul Gortmaker
@ 2016-08-11 9:20 ` Linus Walleij
2016-08-12 0:54 ` Andrew Jeffery
1 sibling, 1 reply; 28+ messages in thread
From: Linus Walleij @ 2016-08-11 9:20 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
> index 25a0ae01429e..a52de9d3adfb 100644
> --- a/arch/arm/mach-aspeed/Kconfig
> +++ b/arch/arm/mach-aspeed/Kconfig
> @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
> select ASPEED_WATCHDOG
> select MOXART_TIMER
> select PINCTRL
> + select GPIOLIB
> + select GPIO_ASPEED
Again this needs to be a separate patch to ARM SoC.
> + select GPIO_SYSFS
NAK over my dead body. I strongly discourage the use of the
GPIO sysfs, use the new character device, see
toos/gpio/* for examples.
> +config GPIO_ASPEED
> + bool "Aspeed GPIO support"
> + depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> + select GENERIC_IRQ_CHIP
Why are you using GENERIC_IRQ_CHIP but not
GPIOLIB_IRQCHIP? Well I guess I may find out by
reading the code...
> + help
> + Say Y here to support Aspeed AST2400 and AST2500 GPIO controllers.
> +
> config GPIO_BCM_KONA
> bool "Broadcom Kona GPIO"
> depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
> @@ -1072,7 +1079,6 @@ config GPIO_SODAVILLE
> select GENERIC_IRQ_CHIP
> help
> Say Y here to support Intel Sodaville GPIO.
> -
> endmenu
Drop this unrelated whitespace change.
> +#define GPIO_BANK(x) ((x) >> 5)
> +#define GPIO_OFFSET(x) ((x) & 0x1f)
> +#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
Clever, maybe needs some comments on how they work?
Or is it obvious from context?
> +#define GPIO_DATA 0x00
> +#define GPIO_DIR 0x04
> +
> +#define GPIO_IRQ_ENABLE 0x00
> +#define GPIO_IRQ_TYPE0 0x04
> +#define GPIO_IRQ_TYPE1 0x08
> +#define GPIO_IRQ_TYPE2 0x0c
> +#define GPIO_IRQ_STATUS 0x10
> +static inline struct aspeed_gpio *to_aspeed_gpio(struct gpio_chip *chip)
> +{
> + return container_of(chip, struct aspeed_gpio, chip);
> +}
NAK rewrite your code to use devm_gpiochip_add_data() and
then use gpiochip_get_data() inline in every function that
needs to get the state container from the gpiochip. Read
the code in the upstream kernel for *any* driver because I
think I changed this virtually everywhere.
(...)
> +static void __aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
Why __underscoring. It is just confusing, drop the underscores.
The function does set the mask.
> +{
> + const struct aspeed_gpio_bank *bank;
> + struct aspeed_gpio *gpio;
> + unsigned long flags;
> + u32 reg, bit;
> + void *addr;
> + int rc;
> +
> + rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
> + if (rc)
> + return;
> +
> + addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
> +
> + spin_lock_irqsave(&gpio->lock, flags);
> +
> + reg = ioread32(addr);
> + if (set)
> + reg |= bit;
> + else
> + reg &= bit;
> + iowrite32(reg, addr);
Hm, if this was done with regmap it would be regmap_update_bits()
simply ... maybe you should just throw a 32bit MMIO regmap over
the registers? (Not required, just an idea to simplify stuff...)
> +static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
> +{
> + u32 type0, type1, type2, bit, reg;
> + const struct aspeed_gpio_bank *bank;
> + irq_flow_handler_t handler;
> + struct aspeed_gpio *gpio;
> + unsigned long flags;
> + void *addr;
> + int rc;
> +
> + rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
> + if (rc)
> + return -EINVAL;
> +
> + type0 = type1 = type2 = 0;
Assign zero when declaring instead:
u32 type0 = 0;
u32 type1 = 0;
...
> +
> + switch (type & IRQ_TYPE_SENSE_MASK) {
> + case IRQ_TYPE_EDGE_BOTH:
> + type2 |= bit;
> + case IRQ_TYPE_EDGE_RISING:
> + type0 |= bit;
> + case IRQ_TYPE_EDGE_FALLING:
> + handler = handle_edge_irq;
> + break;
> + case IRQ_TYPE_LEVEL_HIGH:
> + type0 |= bit;
> + case IRQ_TYPE_LEVEL_LOW:
> + type1 |= bit;
> + handler = handle_level_irq;
> + break;
> + default:
> + return -EINVAL;
> + }
Very nice, this looks exactly as it should, handling the different
IRQs very nicely.
> + spin_lock_irqsave(&gpio->lock, flags);
> +
> + addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
> + reg = ioread32(addr);
> + reg = (reg & ~bit) | type0;
> + iowrite32(reg, addr);
> +
> + addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
> + reg = ioread32(addr);
> + reg = (reg & ~bit) | type1;
> + iowrite32(reg, addr);
> +
> + addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
> + reg = ioread32(addr);
> + reg = (reg & ~bit) | type2;
> + iowrite32(reg, addr);
> +
> + spin_unlock_irqrestore(&gpio->lock, flags);
> +
> + irq_set_handler_locked(d, handler);
> +
> + return 0;
> +}
Overall very nice .set_type().
> +static void aspeed_gpio_irq_handler(struct irq_desc *desc)
> +{
> + struct aspeed_gpio *gpio = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + unsigned int i, p, girq;
> + unsigned long reg;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
> + const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
> +
> + reg = ioread32(bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS));
> +
> + for_each_set_bit(p, ®, 32) {
> + girq = irq_find_mapping(gpio->irq_domain, i * 32 + p);
> + generic_handle_irq(girq);
> + }
> +
> + }
> +
> + chained_irq_exit(chip, desc);
> +}
This looks so generic so I think you should be using
GPIOLIB_IRQCHIP.
> +
> +static struct irq_chip aspeed_gpio_irqchip = {
> + .name = "aspeed-gpio",
> + .irq_ack = aspeed_gpio_irq_ack,
> + .irq_mask = aspeed_gpio_irq_mask,
> + .irq_unmask = aspeed_gpio_irq_unmask,
> + .irq_set_type = aspeed_gpio_set_type,
> +};
There is a missing .request/.release resources marking the lines
as irq to the GPIO core. But if you switch to using GPIOLIB_IRQCHIP
the core will handle all that for you.
> +static int aspeed_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct aspeed_gpio *gpio = to_aspeed_gpio(chip);
> +
> + return irq_find_mapping(gpio->irq_domain, offset);
> +}
> +
> +static void aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
> + struct platform_device *pdev)
> +{
> + int i, irq;
> +
> + /* request our upstream IRQ */
> + gpio->irq = platform_get_irq(pdev, 0);
> + if (gpio->irq < 0)
> + return;
> +
> + /* establish our irq domain to provide IRQs for each extended bank */
> + gpio->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
> + gpio->chip.ngpio, &irq_domain_simple_ops, NULL);
> + if (!gpio->irq_domain)
> + return;
> +
> + for (i = 0; i < gpio->chip.ngpio; i++) {
> + irq = irq_create_mapping(gpio->irq_domain, i);
> + irq_set_chip_data(irq, gpio);
> + irq_set_chip_and_handler(irq, &aspeed_gpio_irqchip,
> + handle_simple_irq);
> + irq_set_probe(irq);
> + }
> +
> + irq_set_chained_handler_and_data(gpio->irq,
> + aspeed_gpio_irq_handler, gpio);
> +}
Also all this goes away with GPILIB_IRQCHIP, so use it.
See e.g. drivers/gpio/gpio-pl061.c for an example of a similar
driver doing this.
> +static int __init aspeed_gpio_probe(struct platform_device *pdev)
> +{
> + struct aspeed_gpio *gpio;
> + struct resource *res;
> + int rc;
> +
> + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> + if (!gpio)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENXIO;
> +
> + gpio->base = devm_ioremap_resource(&pdev->dev, res);
> + if (!gpio->base)
> + return -ENOMEM;
> +
> + spin_lock_init(&gpio->lock);
> +
> + gpio->chip.ngpio = ARRAY_SIZE(aspeed_gpio_banks) * 32;
> +
> + gpio->chip.parent = &pdev->dev;
> + gpio->chip.direction_input = aspeed_gpio_dir_in;
> + gpio->chip.direction_output = aspeed_gpio_dir_out;
Please add gpio->chip.get_direction() to complete the picture.
> + gpio->chip.request = aspeed_gpio_request;
> + gpio->chip.free = aspeed_gpio_free;
> + gpio->chip.get = aspeed_gpio_get;
> + gpio->chip.set = aspeed_gpio_set;
> + gpio->chip.to_irq = aspeed_gpio_to_irq;
.to_irq goes away with GPILIB_IRQCHIP.
> + gpio->chip.label = dev_name(&pdev->dev);
> + gpio->chip.base = -1;
> +
> + platform_set_drvdata(pdev, gpio);
> +
> + rc = gpiochip_add(&gpio->chip);
> + if (rc < 0)
> + return rc;
Use devm_gpiochip_add_data(), then gpiochip_irqchip_add().
> +static int aspeed_gpio_remove(struct platform_device *pdev)
> +{
> + struct aspeed_gpio *gpio = platform_get_drvdata(pdev);
> +
> + gpiochip_remove(&gpio->chip);
> + return 0;
> +}
And then this is not even needed. (devm*)
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-08-11 8:41 ` Linus Walleij
@ 2016-08-12 0:33 ` Andrew Jeffery
2016-08-12 13:18 ` Linus Walleij
0 siblings, 1 reply; 28+ messages in thread
From: Andrew Jeffery @ 2016-08-12 0:33 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2016-08-11 at 10:41 +0200, Linus Walleij wrote:
> On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> >
> > --- a/arch/arm/mach-aspeed/Kconfig
> > +++ b/arch/arm/mach-aspeed/Kconfig
> > @@ -5,6 +5,7 @@ menuconfig ARCH_ASPEED
> > ????????select WATCHDOG
> > ????????select ASPEED_WATCHDOG
> > ????????select MOXART_TIMER
> > +???????select PINCTRL
> > ????????help
> > ??????????Say Y here if you want to run your kernel on an ASpeed BMC SoC.
> This needs to be a separate patch sent to the ARM SoC tree.
> I don't like to merge patches to other subsystems if it can be
> avoided.
Okay, I'll split it out.
>
> >
> > +static inline void aspeed_sig_desc_print_val(
> > +???????????????const struct aspeed_sig_desc *desc, bool enable, u32 rv)
> > +{
> > +#if defined(CONFIG_DEBUG_PINCTRL)
> > +???????pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
> > +???????????????????????desc->mask, enable ? desc->enable : desc->disable,
> > +???????????????????????(rv & desc->mask) >> __ffs(desc->mask), rv);
> > +#endif
> > +}
> You can just use pr_debug(). CONFIG_DEBUG_PINCTRL enables
> DEBUG_KERNEL which activates debug prints so this is a truism.
Right, I will clean that up.
>
> >
> > +static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> > +???????????????bool enabled, struct regmap *map)
> > +static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
> > +???????????????bool enabled, struct regmap *map)
> These need kerneldoc too, they are kind of hard to understand.
Will do.
>
> >
> > +static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
> > +{
> > +???????if (!exprs)
> > +???????????????return false;
> > +
> > +???????while (*exprs) {
> > +???????????????if (strncmp((*exprs)->signal, "GPIO", 4) == 0)
> > +???????????????????????return true;
> This looks a bit fragile and hard to debug. Do you have some better
> idea of how to do this but not resort to string comparison?
Yes, this is a little unfortunate. GPIO is not always a pin's lowest
priority function (e.g. the RGMII/RMII pins), so this makes the GPIO
case like any other mux function: We need to know when to stop
iterating the arrays when disabling mux functions of higher priority.
The alternative is probably to introduce another field to struct
aspeed_sig_expr and set that as necessary, but that feels redundant if
we keep to a consistent naming for the GPIOs.
Would it be acceptable to document that requirement? Maybe that's just
punting on the problem because it doesn't make it any less difficult to
debug. However, the failure case is already tested in
aspeed_gpio_request_enable() (where all aspeed_gpio_in_exprs() calls
fail for a pin) and to make it easier to debug I can dev_warn() at that
point.
I will do both of the above as part of a v2 unless you are really keen
for an alternative.
>
> Apart from that it looks pretty alright, complex but such is life
> with complex hardware.
Mmm, yes. I keep hoping for a day when someone else points out that it
actually has a simple solution so I stop dreading the explanation of
the implementation's mechanics to others.
Anyway, thanks for the review!
Andrew
>
> Yours,
> Linus Walleij
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 06/12] gpio: Add Aspeed driver
2016-08-11 9:20 ` Linus Walleij
@ 2016-08-12 0:54 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-08-12 0:54 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2016-08-11 at 11:20 +0200, Linus Walleij wrote:
> On Wed, Jul 20, 2016 at 7:58 AM, Andrew Jeffery <andrew@aj.id.au>
> wrote:
>
> >
> > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-
> > aspeed/Kconfig
> > index 25a0ae01429e..a52de9d3adfb 100644
> > --- a/arch/arm/mach-aspeed/Kconfig
> > +++ b/arch/arm/mach-aspeed/Kconfig
> > @@ -6,6 +6,10 @@ menuconfig ARCH_ASPEED
> > ????????select ASPEED_WATCHDOG
> > ????????select MOXART_TIMER
> > ????????select PINCTRL
> > +???????select GPIOLIB
> > +???????select GPIO_ASPEED
> Again this needs to be a separate patch to ARM SoC.
>
> >
> > +???????select GPIO_SYSFS
> NAK over my dead body. I strongly discourage the use of the
> GPIO sysfs, use the new character device, see
> toos/gpio/* for examples.
>
> >
> > +config GPIO_ASPEED
> > +???????bool "Aspeed GPIO support"
> > +???????depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> > +???????select GENERIC_IRQ_CHIP
> Why are you using GENERIC_IRQ_CHIP but not
> GPIOLIB_IRQCHIP? Well I guess I may find out by
> reading the code...
>
> >
> > +???????help
> > +?????????Say Y here to support Aspeed AST2400 and AST2500 GPIO
> > controllers.
> > +
> > ?config GPIO_BCM_KONA
> > ????????bool "Broadcom Kona GPIO"
> > ????????depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
> > @@ -1072,7 +1079,6 @@ config GPIO_SODAVILLE
> > ????????select GENERIC_IRQ_CHIP
> > ????????help
> > ??????????Say Y here to support Intel Sodaville GPIO.
> > -
> > ?endmenu
> Drop this unrelated whitespace change.
>
> >
> > +#define GPIO_BANK(x)???((x) >> 5)
> > +#define GPIO_OFFSET(x) ((x) & 0x1f)
> > +#define GPIO_BIT(x)????BIT(GPIO_OFFSET(x))
> Clever, maybe needs some comments on how they work?
> Or is it obvious from context?
>
> >
> > +#define GPIO_DATA??????0x00
> > +#define GPIO_DIR???????0x04
> > +
> > +#define GPIO_IRQ_ENABLE????????0x00
> > +#define GPIO_IRQ_TYPE0 0x04
> > +#define GPIO_IRQ_TYPE1 0x08
> > +#define GPIO_IRQ_TYPE2 0x0c
> > +#define GPIO_IRQ_STATUS????????0x10
> >
> > +static inline struct aspeed_gpio *to_aspeed_gpio(struct gpio_chip
> > *chip)
> > +{
> > +???????return container_of(chip, struct aspeed_gpio, chip);
> > +}
> NAK rewrite your code to use devm_gpiochip_add_data() and
> then use gpiochip_get_data() inline in every function that
> needs to get the state container from the gpiochip. Read
> the code in the upstream kernel for *any* driver because I
> think I changed this virtually everywhere.
>
> (...)
> >
> > +static void __aspeed_gpio_irq_set_mask(struct irq_data *d, bool
> > set)
> Why __underscoring. It is just confusing, drop the underscores.
> The function does set the mask.
>
> >
> > +{
> > +???????const struct aspeed_gpio_bank *bank;
> > +???????struct aspeed_gpio *gpio;
> > +???????unsigned long flags;
> > +???????u32 reg, bit;
> > +???????void *addr;
> > +???????int rc;
> > +
> > +???????rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
> > +???????if (rc)
> > +???????????????return;
> > +
> > +???????addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
> > +
> > +???????spin_lock_irqsave(&gpio->lock, flags);
> > +
> > +???????reg = ioread32(addr);
> > +???????if (set)
> > +???????????????reg |= bit;
> > +???????else
> > +???????????????reg &= bit;
> > +???????iowrite32(reg, addr);
> Hm, if this was done with regmap it would be regmap_update_bits()
> simply ... maybe you should just throw a 32bit MMIO regmap over
> the registers? (Not required, just an idea to simplify stuff...)
>
> >
> > +static int aspeed_gpio_set_type(struct irq_data *d, unsigned int
> > type)
> > +{
> > +???????u32 type0, type1, type2, bit, reg;
> > +???????const struct aspeed_gpio_bank *bank;
> > +???????irq_flow_handler_t handler;
> > +???????struct aspeed_gpio *gpio;
> > +???????unsigned long flags;
> > +???????void *addr;
> > +???????int rc;
> > +
> > +???????rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
> > +???????if (rc)
> > +???????????????return -EINVAL;
> > +
> > +???????type0 = type1 = type2 = 0;
> Assign zero when declaring instead:
>
> u32 type0 = 0;
> u32 type1 = 0;
> ...
>
> >
> > +
> > +???????switch (type & IRQ_TYPE_SENSE_MASK) {
> > +???????case IRQ_TYPE_EDGE_BOTH:
> > +???????????????type2 |= bit;
> > +???????case IRQ_TYPE_EDGE_RISING:
> > +???????????????type0 |= bit;
> > +???????case IRQ_TYPE_EDGE_FALLING:
> > +???????????????handler = handle_edge_irq;
> > +???????????????break;
> > +???????case IRQ_TYPE_LEVEL_HIGH:
> > +???????????????type0 |= bit;
> > +???????case IRQ_TYPE_LEVEL_LOW:
> > +???????????????type1 |= bit;
> > +???????????????handler = handle_level_irq;
> > +???????????????break;
> > +???????default:
> > +???????????????return -EINVAL;
> > +???????}
> Very nice, this looks exactly as it should, handling the different
> IRQs very nicely.
>
> >
> > +???????spin_lock_irqsave(&gpio->lock, flags);
> > +
> > +???????addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
> > +???????reg = ioread32(addr);
> > +???????reg = (reg & ~bit) | type0;
> > +???????iowrite32(reg, addr);
> > +
> > +???????addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
> > +???????reg = ioread32(addr);
> > +???????reg = (reg & ~bit) | type1;
> > +???????iowrite32(reg, addr);
> > +
> > +???????addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
> > +???????reg = ioread32(addr);
> > +???????reg = (reg & ~bit) | type2;
> > +???????iowrite32(reg, addr);
> > +
> > +???????spin_unlock_irqrestore(&gpio->lock, flags);
> > +
> > +???????irq_set_handler_locked(d, handler);
> > +
> > +???????return 0;
> > +}
> Overall very nice .set_type().
>
> >
> > +static void aspeed_gpio_irq_handler(struct irq_desc *desc)
> > +{
> > +???????struct aspeed_gpio *gpio = irq_desc_get_handler_data(desc);
> > +???????struct irq_chip *chip = irq_desc_get_chip(desc);
> > +???????unsigned int i, p, girq;
> > +???????unsigned long reg;
> > +
> > +???????chained_irq_enter(chip, desc);
> > +
> > +???????for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
> > +???????????????const struct aspeed_gpio_bank *bank =
> > &aspeed_gpio_banks[i];
> > +
> > +???????????????reg = ioread32(bank_irq_reg(gpio, bank,
> > GPIO_IRQ_STATUS));
> > +
> > +???????????????for_each_set_bit(p, ®, 32) {
> > +???????????????????????girq = irq_find_mapping(gpio->irq_domain, i
> > * 32 + p);
> > +???????????????????????generic_handle_irq(girq);
> > +???????????????}
> > +
> > +???????}
> > +
> > +???????chained_irq_exit(chip, desc);
> > +}
> This looks so generic so I think you should be using
> GPIOLIB_IRQCHIP.
>
> >
> > +
> > +static struct irq_chip aspeed_gpio_irqchip = {
> > +???????.name???????????= "aspeed-gpio",
> > +???????.irq_ack????????= aspeed_gpio_irq_ack,
> > +???????.irq_mask???????= aspeed_gpio_irq_mask,
> > +???????.irq_unmask?????= aspeed_gpio_irq_unmask,
> > +???????.irq_set_type???= aspeed_gpio_set_type,
> > +};
> There is a missing .request/.release resources marking the lines
> as irq to the GPIO core. But if you switch to using GPIOLIB_IRQCHIP
> the core will handle all that for you.
>
> >
> > +static int aspeed_gpio_to_irq(struct gpio_chip *chip, unsigned int
> > offset)
> > +{
> > +???????struct aspeed_gpio *gpio = to_aspeed_gpio(chip);
> > +
> > +???????return irq_find_mapping(gpio->irq_domain, offset);
> > +}
> > +
> > +static void aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
> > +???????????????struct platform_device *pdev)
> > +{
> > +???????int i, irq;
> > +
> > +???????/* request our upstream IRQ */
> > +???????gpio->irq = platform_get_irq(pdev, 0);
> > +???????if (gpio->irq < 0)
> > +???????????????return;
> > +
> > +???????/* establish our irq domain to provide IRQs for each
> > extended bank */
> > +???????gpio->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
> > +???????????????????????gpio->chip.ngpio, &irq_domain_simple_ops,
> > NULL);
> > +???????if (!gpio->irq_domain)
> > +???????????????return;
> > +
> > +???????for (i = 0; i < gpio->chip.ngpio; i++) {
> > +???????????????irq = irq_create_mapping(gpio->irq_domain, i);
> > +???????????????irq_set_chip_data(irq, gpio);
> > +???????????????irq_set_chip_and_handler(irq, &aspeed_gpio_irqchip,
> > +???????????????????????????????handle_simple_irq);
> > +???????????????irq_set_probe(irq);
> > +???????}
> > +
> > +???????irq_set_chained_handler_and_data(gpio->irq,
> > +???????????????????????aspeed_gpio_irq_handler, gpio);
> > +}
> Also all this goes away with GPILIB_IRQCHIP, so use it.
>
> See e.g. drivers/gpio/gpio-pl061.c for an example of a similar
> driver doing this.
>
> >
> > +static int __init aspeed_gpio_probe(struct platform_device *pdev)
> > +{
> > +???????struct aspeed_gpio *gpio;
> > +???????struct resource *res;
> > +???????int rc;
> > +
> > +???????gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> > +???????if (!gpio)
> > +???????????????return -ENOMEM;
> > +
> > +???????res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +???????if (!res)
> > +???????????????return -ENXIO;
> > +
> > +???????gpio->base = devm_ioremap_resource(&pdev->dev, res);
> > +???????if (!gpio->base)
> > +???????????????return -ENOMEM;
> > +
> > +???????spin_lock_init(&gpio->lock);
> > +
> > +???????gpio->chip.ngpio = ARRAY_SIZE(aspeed_gpio_banks) * 32;
> > +
> > +???????gpio->chip.parent = &pdev->dev;
> > +???????gpio->chip.direction_input = aspeed_gpio_dir_in;
> > +???????gpio->chip.direction_output = aspeed_gpio_dir_out;
> Please add gpio->chip.get_direction() to complete the picture.
>
> >
> > +???????gpio->chip.request = aspeed_gpio_request;
> > +???????gpio->chip.free = aspeed_gpio_free;
> > +???????gpio->chip.get = aspeed_gpio_get;
> > +???????gpio->chip.set = aspeed_gpio_set;
> > +???????gpio->chip.to_irq = aspeed_gpio_to_irq;
> .to_irq goes away with GPILIB_IRQCHIP.
>
> >
> > +???????gpio->chip.label = dev_name(&pdev->dev);
> > +???????gpio->chip.base = -1;
> > +
> > +???????platform_set_drvdata(pdev, gpio);
> > +
> > +???????rc = gpiochip_add(&gpio->chip);
> > +???????if (rc < 0)
> > +???????????????return rc;
> Use devm_gpiochip_add_data(), then gpiochip_irqchip_add().
>
> >
> > +static int aspeed_gpio_remove(struct platform_device *pdev)
> > +{
> > +???????struct aspeed_gpio *gpio = platform_get_drvdata(pdev);
> > +
> > +???????gpiochip_remove(&gpio->chip);
> > +???????return 0;
> > +}
> And then this is not even needed. (devm*)
>
> Yours,
> Linus Walleij
Thanks, I will clean up the issues. I brought the patch into the series
because I figured that's what made sense. I should have looked at it a
bit closer.
Cheers,
Andrew
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-08-12 0:33 ` Andrew Jeffery
@ 2016-08-12 13:18 ` Linus Walleij
2016-08-13 0:58 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 28+ messages in thread
From: Linus Walleij @ 2016-08-12 13:18 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 12, 2016 at 2:33 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
>> > +
>> > + while (*exprs) {
>> > + if (strncmp((*exprs)->signal, "GPIO", 4) == 0)
>> > + return true;
>> This looks a bit fragile and hard to debug. Do you have some better
>> idea of how to do this but not resort to string comparison?
>
> Yes, this is a little unfortunate. GPIO is not always a pin's lowest
> priority function (e.g. the RGMII/RMII pins), so this makes the GPIO
> case like any other mux function: We need to know when to stop
> iterating the arrays when disabling mux functions of higher priority.
> The alternative is probably to introduce another field to struct
> aspeed_sig_expr and set that as necessary, but that feels redundant if
> we keep to a consistent naming for the GPIOs.
I would probably prefer that option (introduce another field)
but you should make the overall decision, it's no strong opinion
from my side.
> Would it be acceptable to document that requirement?
Sure.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-08-12 13:18 ` Linus Walleij
@ 2016-08-13 0:58 ` Benjamin Herrenschmidt
2016-08-15 0:36 ` Andrew Jeffery
0 siblings, 1 reply; 28+ messages in thread
From: Benjamin Herrenschmidt @ 2016-08-13 0:58 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 2016-08-12 at 15:18 +0200, Linus Walleij wrote:
> I would probably prefer that option (introduce another field)
> but you should make the overall decision, it's no strong opinion
> from my side.
>
> > Would it be acceptable to document that requirement?
It might make it a bit less nasty (and easier to change later on
if necessary) to use some kind of:
bool ast_signal_is_gpio(...)
And stick the strcmp in there.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs
2016-08-13 0:58 ` Benjamin Herrenschmidt
@ 2016-08-15 0:36 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2016-08-15 0:36 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, 2016-08-13 at 10:58 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2016-08-12 at 15:18 +0200, Linus Walleij wrote:
> >
> > I would probably prefer that option (introduce another field)
> > but you should make the overall decision, it's no strong opinion
> > from my side.
> >
> > >
> > > Would it be acceptable to document that requirement?
> It might make it a bit less nasty (and easier to change later on
> if necessary) to use some kind of:
>
> bool ast_signal_is_gpio(...)
>
> And stick the strcmp in there.
Yep, I'll do so for v2.
Cheers,
Andrew
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2016-08-15 0:36 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-20 5:58 [PATCH 00/12] aspeed: Add pinctrl and gpio drivers Andrew Jeffery
2016-07-20 5:58 ` [PATCH 01/12] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Andrew Jeffery
2016-07-20 19:05 ` Rob Herring
2016-07-20 23:13 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs Andrew Jeffery
2016-07-22 6:29 ` Joel Stanley
2016-08-11 8:41 ` Linus Walleij
2016-08-12 0:33 ` Andrew Jeffery
2016-08-12 13:18 ` Linus Walleij
2016-08-13 0:58 ` Benjamin Herrenschmidt
2016-08-15 0:36 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 03/12] pinctrl: Add pinctrl-aspeed-g4 driver Andrew Jeffery
2016-07-20 5:58 ` [PATCH 04/12] pinctrl: Add pinctrl-aspeed-g5 driver Andrew Jeffery
2016-07-20 5:58 ` [PATCH 05/12] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers Andrew Jeffery
2016-07-20 19:06 ` Rob Herring
2016-07-20 5:58 ` [PATCH 06/12] gpio: Add Aspeed driver Andrew Jeffery
2016-07-21 20:12 ` Paul Gortmaker
2016-07-22 0:49 ` Andrew Jeffery
2016-08-11 9:20 ` Linus Walleij
2016-08-12 0:54 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 07/12] syscon: dt-bindings: Add documentation for Aspeed system control units Andrew Jeffery
2016-07-20 19:09 ` Rob Herring
2016-07-21 1:04 ` Andrew Jeffery
2016-07-20 5:58 ` [PATCH 08/12] aspeed-g4: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20 5:58 ` [PATCH 09/12] palmetto: Request relevant mux functions in devicetree Andrew Jeffery
2016-07-20 5:58 ` [PATCH 10/12] aspeed-g4: Add gpio controller to devicetree Andrew Jeffery
2016-07-20 5:58 ` [PATCH 11/12] aspeed-g5: Add syscon and pin controller nodes Andrew Jeffery
2016-07-20 5:58 ` [PATCH 12/12] aspeed-g5: Add gpio controller to devicetree Andrew Jeffery
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