From mboxrd@z Thu Jan 1 00:00:00 1970 From: lina.iyer@linaro.org (Lina Iyer) Date: Fri, 26 Aug 2016 14:17:57 -0600 Subject: [PATCH v5 15/16] dt/bindings: Add PSCI OS-Initiated PM Domains bindings In-Reply-To: <1472242678-33700-1-git-send-email-lina.iyer@linaro.org> References: <1472242678-33700-1-git-send-email-lina.iyer@linaro.org> Message-ID: <1472242678-33700-16-git-send-email-lina.iyer@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add bindings for defining a OS-Initiated based CPU PM domain. Cc: Cc: Lorenzo Pieralisi Cc: Mark Rutland Signed-off-by: Lina Iyer --- Documentation/devicetree/bindings/arm/psci.txt | 79 ++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d..63a229b 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,86 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPU domains +from the firmware. Such PM domains for which the PSCI firmware driver acts as +pseudo-controller, may also be specified in the DT under the psci node. The +domain definitions must follow the domain idle state specifications per [3]. +The domain states themselves must be compatible with 'arm,idle-state' defined +in [1] and need to specify the arm,psci-suspend-param property for each idle +state. + +More information on defining CPU PM domains is available in [4]. + +Example: OS-Iniated PSCI based PM domains with 1 CPU in each domain + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>; + power-domains = <&CPU_PD0>; + }; + + CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>; + power-domains = <&CPU_PD1>; + }; + + idle-states { + CPU_PWRDN: cpu_power_down{ + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: domain_ret { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWR_DWN: domain_gdhs { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd at 0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>; + }; + + CPU_PD1: cpu-pd at 1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DWN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt +[4]. CPU PM Domains description + Documentation/power/cpu_domains.txt -- 2.7.4