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From: Bhupesh Sharma <bhsharma@redhat.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, steve.capper@arm.com,
	catalin.marinas@arm.com, bhsharma@redhat.com,
	ard.biesheuvel@linaro.org, will.deacon@arm.com,
	bhupesh.linux@gmail.com, kexec@lists.infradead.org,
	suzuki.poulose@arm.com
Subject: [PATCH 2/2] arm64: Expose PARange via ID_AA64MMFR0_EL1 and VARange via ID_AA64MMFR2_EL1
Date: Tue, 29 Jan 2019 02:27:56 +0530
Message-ID: <1548709076-22317-3-git-send-email-bhsharma@redhat.com> (raw)
In-Reply-To: <1548709076-22317-1-git-send-email-bhsharma@redhat.com>

ARMv8.2 architecture hardware extensions can support
upto 52-bit physical addresses (ARMv8.2-LPA) and 52-bit virtual
addresses (ARMv8.2-LVA).

User-space utilities like 'makedumpfile' can try and use the getauxval()
function to retrieve the underlying PARange and VARange values
supported.

An example implementation can be via the 'Appendix I: Example' shown
in 'Documentation/arm64/cpu-feature-registers.txt'. A reference
'makedumpfile' implementation which uses a similar approach is
available in [0].

So, we expose these properties via 'FTR_NONSTRICT' and 'FTR_VISIBLE'
settings for 'ID_AA64MMFR0_PARANGE_SHIFT' and 'ID_AA64MMFR2_LVA_SHIFT'.

[0]. https://github.com/bhupesh-sharma/makedumpfile/blob/9d7da4aad3efe79b448f48cc3454fcae46a316d6/arch/arm64.c#L499

Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
---
 arch/arm64/kernel/cpufeature.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f6d84e2c92fe..5cfc08cbf147 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -194,7 +194,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 	 * Differing PARange is fine as long as all peripherals and memory are mapped
 	 * within the minimum PARange of all CPUs
 	 */
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 	ARM64_FTR_END,
 };
 
@@ -211,7 +211,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
-- 
2.7.4


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  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-28 20:57 [PATCH 0/2] arm64: Expose physical and virtual address capabilities to user-space Bhupesh Sharma
2019-01-28 20:57 ` [PATCH 1/2] arm64: Expose address bits (physical/virtual) via cpuinfo Bhupesh Sharma
2019-01-29 10:09   ` Suzuki K Poulose
2019-01-30 19:48     ` Bhupesh Sharma
2019-02-04 16:54       ` James Morse
2019-01-28 20:57 ` Bhupesh Sharma [this message]
2019-01-29 10:14   ` [PATCH 2/2] arm64: Expose PARange via ID_AA64MMFR0_EL1 and VARange via ID_AA64MMFR2_EL1 Suzuki K Poulose
2019-01-30 20:27     ` Bhupesh Sharma

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