From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
Jeremy Linton <jeremy.linton@arm.com>,
Shaokun Zhang <zhangshaokun@hisilicon.com>,
Sudeep Holla <sudeep.holla@arm.com>
Subject: [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size
Date: Tue, 28 May 2019 10:16:53 +0800 [thread overview]
Message-ID: <1559009814-17004-1-git-send-email-zhangshaokun@hisilicon.com> (raw)
Add coherency_max_size variable to record the maximum cache line size
for different cache levels. If it is available, we will synchronize
it as cache line size, otherwise we will use CTR_EL0.CWG reporting
in cache_line_size() for arm64.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
ChangeLog since v3:
-- Address Greg's comments
-- Fix some commit information
ChangeLog since v2:
-- Rebase to 5.2-rc2
-- Export cache_line_size for I/O driver
ChangeLog since v1:
-- Move coherency_max_size to drivers/base/cacheinfo.c
-- Address Catalin's comments
Link: https://www.spinics.net/lists/arm-kernel/msg723615.html
drivers/base/cacheinfo.c | 5 +++++
include/linux/cacheinfo.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index a7359535caf5..8827c60f51e2 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu)
return -ENOTSUPP;
}
+unsigned int coherency_max_size;
+
static int cache_shared_cpu_map_setup(unsigned int cpu)
{
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
@@ -251,6 +253,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
}
}
+ /* record the maximum cache line size */
+ if (this_leaf->coherency_line_size > coherency_max_size)
+ coherency_max_size = this_leaf->coherency_line_size;
}
return 0;
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 70e19bc6cc9f..46b92cd61d0c 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -17,6 +17,8 @@ enum cache_type {
CACHE_TYPE_UNIFIED = BIT(2),
};
+extern unsigned int coherency_max_size;
+
/**
* struct cacheinfo - represent a cache leaf node
* @id: This cache's id. It is unique among caches with the same (type, level).
--
2.7.4
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next reply other threads:[~2019-05-28 2:18 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 2:16 Shaokun Zhang [this message]
2019-05-28 2:16 ` [PATCH v4 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Shaokun Zhang
2019-06-03 9:31 ` [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size Greg Kroah-Hartman
2019-06-04 12:45 ` Catalin Marinas
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