* [PATCH 1/5] serial: stm32: add support of timeout interrupt for RX
2019-06-18 10:02 [PATCH 0/5] STM32 usart FIFO handling Erwan Le Ray
@ 2019-06-18 10:02 ` Erwan Le Ray
2019-06-18 10:02 ` [PATCH 2/5] serial: stm32: update PIO transmission Erwan Le Ray
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Erwan Le Ray @ 2019-06-18 10:02 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, Erwan Le Ray, linux-serial, Gerald Baeza,
Fabrice Gasnier, linux-stm32, linux-arm-kernel
Add support of RX timeout interrupts to limit the number of interrupts.
RX timeout is a number of bits (baud clock cycles) without
transmission seen in the receiver. One character is used as an arbitrary
RX timeout value.
If parity is enabled, the number of bits has to include parity bit.
Signed-off-by: Gerald Baeza <gerald.baeza@st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 9c2b04e..e1cfb1e 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -437,6 +437,10 @@ static irqreturn_t stm32_interrupt(int irq, void *ptr)
sr = readl_relaxed(port->membase + ofs->isr);
+ if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
+ writel_relaxed(USART_ICR_RTOCF,
+ port->membase + ofs->icr);
+
if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
writel_relaxed(USART_ICR_WUCF,
port->membase + ofs->icr);
@@ -523,7 +527,7 @@ static void stm32_throttle(struct uart_port *port)
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
- stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
+ stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -535,7 +539,7 @@ static void stm32_unthrottle(struct uart_port *port)
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
- stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
+ stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -545,7 +549,7 @@ static void stm32_stop_rx(struct uart_port *port)
struct stm32_port *stm32_port = to_stm32_port(port);
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
- stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
+ stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
}
/* Handle breaks - ignored by us */
@@ -567,7 +571,7 @@ static int stm32_startup(struct uart_port *port)
if (ret)
return ret;
- val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
+ val = stm32_port->cr1_irq | USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
val |= USART_CR1_FIFOEN;
stm32_set_bits(port, ofs->cr1, val);
@@ -583,7 +587,8 @@ static void stm32_shutdown(struct uart_port *port)
u32 val, isr;
int ret;
- val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
+ val = USART_CR1_TXEIE | USART_CR1_TE;
+ val |= stm32_port->cr1_irq | USART_CR1_RE;
val |= BIT(cfg->uart_enable_bit);
if (stm32_port->fifoen)
val |= USART_CR1_FIFOEN;
@@ -653,7 +658,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
/* Stop serial port and reset value */
writel_relaxed(0, port->membase + ofs->cr1);
- cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
+ cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
@@ -686,6 +691,19 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
, bits);
+ if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
+ stm32_port->fifoen)) {
+ if (cflag & CSTOPB)
+ bits = bits + 3; /* 1 start bit + 2 stop bits */
+ else
+ bits = bits + 2; /* 1 start bit + 1 stop bit */
+
+ /* RX timeout irq to occur after last stop bit + bits */
+ stm32_port->cr1_irq = USART_CR1_RTOIE;
+ writel_relaxed(bits, port->membase + ofs->rtor);
+ cr2 |= USART_CR2_RTOEN;
+ }
+
if (cflag & PARODD)
cr1 |= USART_CR1_PS;
@@ -925,6 +943,7 @@ static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
stm32_ports[id].hw_flow_control = of_property_read_bool(np,
"st,hw-flow-ctrl");
stm32_ports[id].port.line = id;
+ stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
stm32_ports[id].last_res = RX_BUF_L;
return &stm32_ports[id];
}
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index 30d2433..fcd01fe 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -249,6 +249,7 @@ struct stm32_port {
struct dma_chan *tx_ch; /* dma tx channel */
dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
unsigned char *tx_buf; /* dma tx buffer cpu address */
+ u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
int last_res;
bool tx_dma_busy; /* dma tx busy */
bool hw_flow_control;
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/5] serial: stm32: update PIO transmission
2019-06-18 10:02 [PATCH 0/5] STM32 usart FIFO handling Erwan Le Ray
2019-06-18 10:02 ` [PATCH 1/5] serial: stm32: add support of timeout interrupt for RX Erwan Le Ray
@ 2019-06-18 10:02 ` Erwan Le Ray
2019-06-18 10:02 ` [PATCH 3/5] serial: stm32: add support of TX FIFO threshold Erwan Le Ray
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Erwan Le Ray @ 2019-06-18 10:02 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, Erwan Le Ray, linux-serial, Fabrice Gasnier,
linux-stm32, linux-arm-kernel
Improves PIO transmission:
- Replaces the FIFO filling per character by a filling per blocks of
characters, which provides better performances
- Replaces the active waiting loop by TX empty interrupt dynamic handling.
TXE interrupt is now enabled when data has to be sent (ie when
uart_circ is not empty), and inhibited when there is no more data to
send (ie when uart_circ is empty).
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index e1cfb1e..8316e19 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -303,27 +303,26 @@ static void stm32_transmit_chars_pio(struct uart_port *port)
struct stm32_port *stm32_port = to_stm32_port(port);
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
struct circ_buf *xmit = &port->state->xmit;
- unsigned int isr;
- int ret;
if (stm32_port->tx_dma_busy) {
stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
stm32_port->tx_dma_busy = false;
}
- ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
- isr,
- (isr & USART_SR_TXE),
- 10, 100000);
-
- if (ret)
- dev_err(port->dev, "tx empty not set\n");
-
- stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ while (!uart_circ_empty(xmit)) {
+ /* Check that TDR is empty before filling FIFO */
+ if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
+ break;
+ writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ }
- writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
- port->icount.tx++;
+ /* rely on TXE irq (mask or unmask) for sending remaining data */
+ if (uart_circ_empty(xmit))
+ stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ else
+ stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
}
static void stm32_transmit_chars_dma(struct uart_port *port)
--
1.9.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/5] serial: stm32: add support of TX FIFO threshold
2019-06-18 10:02 [PATCH 0/5] STM32 usart FIFO handling Erwan Le Ray
2019-06-18 10:02 ` [PATCH 1/5] serial: stm32: add support of timeout interrupt for RX Erwan Le Ray
2019-06-18 10:02 ` [PATCH 2/5] serial: stm32: update PIO transmission Erwan Le Ray
@ 2019-06-18 10:02 ` Erwan Le Ray
2019-06-18 10:02 ` [PATCH 4/5] serial: stm32: add support of RX " Erwan Le Ray
2019-06-18 10:02 ` [PATCH 5/5] serial: stm32: add RX and TX FIFO flush Erwan Le Ray
4 siblings, 0 replies; 6+ messages in thread
From: Erwan Le Ray @ 2019-06-18 10:02 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, Erwan Le Ray, linux-serial, Fabrice Gasnier,
linux-stm32, linux-arm-kernel
Adds the support of TX FIFO threshold in order to improve the TX FIFO
management:
- TX FIFO threshold irq enabling (instead of relying on tx empty / fifo
not full irq that generates one irq/char)
- TXCFG is set to half fifo size (e.g. 16/2 = 8 data for a 16 data depth
FIFO)
- irq rate may be reduced by up to 1/TXCFG, e.g. 1 over 8 with current
TXCFG setting.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 8316e19..397d86d 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -298,6 +298,32 @@ static void stm32_tx_dma_complete(void *arg)
stm32_transmit_chars(port);
}
+static void stm32_tx_interrupt_enable(struct uart_port *port)
+{
+ struct stm32_port *stm32_port = to_stm32_port(port);
+ struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
+
+ /*
+ * Enables TX FIFO threashold irq when FIFO is enabled,
+ * or TX empty irq when FIFO is disabled
+ */
+ if (stm32_port->fifoen)
+ stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
+ else
+ stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
+}
+
+static void stm32_tx_interrupt_disable(struct uart_port *port)
+{
+ struct stm32_port *stm32_port = to_stm32_port(port);
+ struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
+
+ if (stm32_port->fifoen)
+ stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
+ else
+ stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+}
+
static void stm32_transmit_chars_pio(struct uart_port *port)
{
struct stm32_port *stm32_port = to_stm32_port(port);
@@ -320,9 +346,9 @@ static void stm32_transmit_chars_pio(struct uart_port *port)
/* rely on TXE irq (mask or unmask) for sending remaining data */
if (uart_circ_empty(xmit))
- stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ stm32_tx_interrupt_disable(port);
else
- stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ stm32_tx_interrupt_enable(port);
}
static void stm32_transmit_chars_dma(struct uart_port *port)
@@ -404,7 +430,7 @@ static void stm32_transmit_chars(struct uart_port *port)
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
- stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ stm32_tx_interrupt_disable(port);
return;
}
@@ -422,7 +448,7 @@ static void stm32_transmit_chars(struct uart_port *port)
uart_write_wakeup(port);
if (uart_circ_empty(xmit))
- stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ stm32_tx_interrupt_disable(port);
}
static irqreturn_t stm32_interrupt(int irq, void *ptr)
@@ -501,10 +527,7 @@ static unsigned int stm32_get_mctrl(struct uart_port *port)
/* Transmit stop */
static void stm32_stop_tx(struct uart_port *port)
{
- struct stm32_port *stm32_port = to_stm32_port(port);
- struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
-
- stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
+ stm32_tx_interrupt_disable(port);
}
/* There are probably characters waiting to be transmitted. */
@@ -575,6 +598,13 @@ static int stm32_startup(struct uart_port *port)
val |= USART_CR1_FIFOEN;
stm32_set_bits(port, ofs->cr1, val);
+ if (stm32_port->fifoen) {
+ val = readl_relaxed(port->membase + ofs->cr3);
+ val &= ~USART_CR3_TXFTCFG_MASK;
+ val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
+ writel_relaxed(val, port->membase + ofs->cr3);
+ }
+
return 0;
}
@@ -662,7 +692,9 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
cr2 = 0;
- cr3 = 0;
+ cr3 = readl_relaxed(port->membase + ofs->cr3);
+ cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG | USART_CR3_RXFTIE
+ | USART_CR3_TXFTCFG_MASK;
if (cflag & CSTOPB)
cr2 |= USART_CR2_STOP_2B;
@@ -869,6 +901,7 @@ static int stm32_init_port(struct stm32_port *stm32port,
port->flags = UPF_BOOT_AUTOCONF;
port->ops = &stm32_uart_ops;
port->dev = &pdev->dev;
+ port->fifosize = stm32port->info->cfg.fifosize;
ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index fcd01fe..a598446 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -27,6 +27,7 @@ struct stm32_usart_config {
bool has_7bits_data;
bool has_wakeup;
bool has_fifo;
+ int fifosize;
};
struct stm32_usart_info {
@@ -54,6 +55,7 @@ struct stm32_usart_info stm32f4_info = {
.cfg = {
.uart_enable_bit = 13,
.has_7bits_data = false,
+ .fifosize = 1,
}
};
@@ -74,6 +76,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+ .fifosize = 1,
}
};
@@ -96,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.has_7bits_data = true,
.has_wakeup = true,
.has_fifo = true,
+ .fifosize = 16,
}
};
@@ -204,6 +208,15 @@ struct stm32_usart_info stm32h7_info = {
#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */
#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */
#define USART_CR3_WUFIE BIT(22) /* H7 */
+#define USART_CR3_TXFTIE BIT(23) /* H7 */
+#define USART_CR3_TCBGTIE BIT(24) /* H7 */
+#define USART_CR3_RXFTCFG GENMASK(27, 25) /* H7 */
+#define USART_CR3_RXFTIE BIT(28) /* H7 */
+#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */
+#define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */
+
+/* TX FIFO threashold set to half of its depth */
+#define USART_CR3_TXFTCFG_HALF 0x2
/* USART_GTPR */
#define USART_GTPR_PSC_MASK GENMASK(7, 0)
--
1.9.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/5] serial: stm32: add support of RX FIFO threshold
2019-06-18 10:02 [PATCH 0/5] STM32 usart FIFO handling Erwan Le Ray
` (2 preceding siblings ...)
2019-06-18 10:02 ` [PATCH 3/5] serial: stm32: add support of TX FIFO threshold Erwan Le Ray
@ 2019-06-18 10:02 ` Erwan Le Ray
2019-06-18 10:02 ` [PATCH 5/5] serial: stm32: add RX and TX FIFO flush Erwan Le Ray
4 siblings, 0 replies; 6+ messages in thread
From: Erwan Le Ray @ 2019-06-18 10:02 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, Erwan Le Ray, linux-serial, Fabrice Gasnier,
linux-stm32, linux-arm-kernel
Adds the support of RX FIFO threshold in order to improve the RX FIFO
management.
This is done by enabling fifo threshold interrupt, instead of relying
on rx empty/fifo not full irq. That basically generates one irq/char
currently. With this patch:
- RXCFG is set to half fifo size (e.g. 16/2 = 8 data for a 16 data depth
FIFO)
- irq rate may be reduced by up to 1/RXCFG, e.g. 1 over 8 with current
RXCFG setting.
- Receiver timeout is used to gather chars when FIFO threshold isn't
reached.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 397d86d..4083145 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -550,6 +550,9 @@ static void stm32_throttle(struct uart_port *port)
spin_lock_irqsave(&port->lock, flags);
stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
+ if (stm32_port->cr3_irq)
+ stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
+
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -562,6 +565,9 @@ static void stm32_unthrottle(struct uart_port *port)
spin_lock_irqsave(&port->lock, flags);
stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
+ if (stm32_port->cr3_irq)
+ stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
+
spin_unlock_irqrestore(&port->lock, flags);
}
@@ -572,6 +578,9 @@ static void stm32_stop_rx(struct uart_port *port)
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
+ if (stm32_port->cr3_irq)
+ stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
+
}
/* Handle breaks - ignored by us */
@@ -600,8 +609,9 @@ static int stm32_startup(struct uart_port *port)
if (stm32_port->fifoen) {
val = readl_relaxed(port->membase + ofs->cr3);
- val &= ~USART_CR3_TXFTCFG_MASK;
+ val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
+ val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
writel_relaxed(val, port->membase + ofs->cr3);
}
@@ -693,7 +703,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
cr1 |= USART_CR1_FIFOEN;
cr2 = 0;
cr3 = readl_relaxed(port->membase + ofs->cr3);
- cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG | USART_CR3_RXFTIE
+ cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
| USART_CR3_TXFTCFG_MASK;
if (cflag & CSTOPB)
@@ -733,8 +743,14 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
stm32_port->cr1_irq = USART_CR1_RTOIE;
writel_relaxed(bits, port->membase + ofs->rtor);
cr2 |= USART_CR2_RTOEN;
+ /* Not using dma, enable fifo threshold irq */
+ if (!stm32_port->rx_ch)
+ stm32_port->cr3_irq = USART_CR3_RXFTIE;
}
+ cr1 |= stm32_port->cr1_irq;
+ cr3 |= stm32_port->cr3_irq;
+
if (cflag & PARODD)
cr1 |= USART_CR1_PS;
@@ -976,6 +992,7 @@ static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
"st,hw-flow-ctrl");
stm32_ports[id].port.line = id;
stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
+ stm32_ports[id].cr3_irq = 0;
stm32_ports[id].last_res = RX_BUF_L;
return &stm32_ports[id];
}
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index a598446..a175c10 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -210,7 +210,8 @@ struct stm32_usart_info stm32h7_info = {
#define USART_CR3_WUFIE BIT(22) /* H7 */
#define USART_CR3_TXFTIE BIT(23) /* H7 */
#define USART_CR3_TCBGTIE BIT(24) /* H7 */
-#define USART_CR3_RXFTCFG GENMASK(27, 25) /* H7 */
+#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */
+#define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */
#define USART_CR3_RXFTIE BIT(28) /* H7 */
#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */
#define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */
@@ -218,6 +219,9 @@ struct stm32_usart_info stm32h7_info = {
/* TX FIFO threashold set to half of its depth */
#define USART_CR3_TXFTCFG_HALF 0x2
+/* RX FIFO threashold set to half of its depth */
+#define USART_CR3_RXFTCFG_HALF 0x2
+
/* USART_GTPR */
#define USART_GTPR_PSC_MASK GENMASK(7, 0)
#define USART_GTPR_GT_MASK GENMASK(15, 8)
@@ -263,6 +267,7 @@ struct stm32_port {
dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
unsigned char *tx_buf; /* dma tx buffer cpu address */
u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
+ u32 cr3_irq; /* USART_CR3_RXFTIE */
int last_res;
bool tx_dma_busy; /* dma tx busy */
bool hw_flow_control;
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 5/5] serial: stm32: add RX and TX FIFO flush
2019-06-18 10:02 [PATCH 0/5] STM32 usart FIFO handling Erwan Le Ray
` (3 preceding siblings ...)
2019-06-18 10:02 ` [PATCH 4/5] serial: stm32: add support of RX " Erwan Le Ray
@ 2019-06-18 10:02 ` Erwan Le Ray
4 siblings, 0 replies; 6+ messages in thread
From: Erwan Le Ray @ 2019-06-18 10:02 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, Erwan Le Ray, linux-serial, Fabrice Gasnier,
linux-stm32, linux-arm-kernel
Adds a flush of RX and TX FIFOs, and fixes some errors:
- adds RX FIFO flush in startup fonction
- removes the useless transmitter enabling in startup fonction
(e.g. receiver only, see Documentation/serial/driver)
- configures FIFO threshold before enabling it, rather than after
- flushes both TX and RX in set_termios function
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 4083145..21dc380 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -602,11 +602,11 @@ static int stm32_startup(struct uart_port *port)
if (ret)
return ret;
- val = stm32_port->cr1_irq | USART_CR1_TE | USART_CR1_RE;
- if (stm32_port->fifoen)
- val |= USART_CR1_FIFOEN;
- stm32_set_bits(port, ofs->cr1, val);
+ /* RX FIFO Flush */
+ if (ofs->rqr != UNDEF_REG)
+ stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
+ /* Tx and RX FIFO configuration */
if (stm32_port->fifoen) {
val = readl_relaxed(port->membase + ofs->cr3);
val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
@@ -615,6 +615,12 @@ static int stm32_startup(struct uart_port *port)
writel_relaxed(val, port->membase + ofs->cr3);
}
+ /* RX FIFO enabling */
+ val = stm32_port->cr1_irq | USART_CR1_RE;
+ if (stm32_port->fifoen)
+ val |= USART_CR1_FIFOEN;
+ stm32_set_bits(port, ofs->cr1, val);
+
return 0;
}
@@ -697,8 +703,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
/* Stop serial port and reset value */
writel_relaxed(0, port->membase + ofs->cr1);
- cr1 = USART_CR1_TE | USART_CR1_RE;
+ /* flush RX & TX FIFO */
+ if (ofs->rqr != UNDEF_REG)
+ stm32_set_bits(port, ofs->rqr,
+ USART_RQR_TXFRQ | USART_RQR_RXFRQ);
+ cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
cr2 = 0;
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread