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From: CK Hu <ck.hu@mediatek.com>
To: Jitao Shi <jitao.shi@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>,
	stonea168@163.com, dri-devel@lists.freedesktop.org,
	yingjoe.chen@mediatek.com, Ajay Kumar <ajaykumar.rs@samsung.com>,
	Vincent Palatin <vpalatin@chromium.org>,
	cawa.cheng@mediatek.com, bibby.hsieh@mediatek.com,
	Russell King <rmk+kernel@arm.linux.org.uk>,
	Thierry Reding <treding@nvidia.com>,
	linux-pwm@vger.kernel.org, Sascha Hauer <kernel@pengutronix.de>,
	Pawel Moll <pawel.moll@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Inki Dae <inki.dae@samsung.com>, Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Andy Yan <andy.yan@rock-chips.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org,
	Rahul Sharma <rahul.sharma@samsung.com>,
	srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Sean Paul <seanpaul@chromium.org>
Subject: Re: [v5 4/7] drm/mediatek: add frame size control
Date: Mon, 1 Jul 2019 09:29:22 +0800	[thread overview]
Message-ID: <1561944562.17120.1.camel@mtksdaap41> (raw)
In-Reply-To: <20190627080116.40264-5-jitao.shi@mediatek.com>

Hi, Jitao:

On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>

This version is different than previous version, so you should remove
the reviewed-by tag. For this version, I still give you a

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 6b6550926db6..45e331055842 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -78,6 +78,7 @@
>  #define DSI_VBP_NL		0x24
>  #define DSI_VFP_NL		0x28
>  #define DSI_VACT_NL		0x2C
> +#define DSI_SIZE_CON		0x38
>  #define DSI_HSA_WC		0x50
>  #define DSI_HBP_WC		0x54
>  #define DSI_HFP_WC		0x58
> @@ -162,6 +163,7 @@ struct phy;
>  struct mtk_dsi_driver_data {
>  	const u32 reg_cmdq_off;
>  	bool has_shadow_ctl;
> +	bool has_size_ctl;
>  };
>  
>  struct mtk_dsi {
> @@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>  	writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
>  	writel(vm->vactive, dsi->regs + DSI_VACT_NL);
>  
> +	if (dsi->driver_data->has_size_ctl)
> +		writel(vm->vactive << 16 | vm->hactive,
> +		       dsi->regs + DSI_SIZE_CON);
> +
>  	horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
>  
>  	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)



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  reply	other threads:[~2019-07-01  1:30 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-27  8:01 [v5 0/7] Support dsi for mt8183 Jitao Shi
2019-06-27  8:01 ` [v5 1/7] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-06-28  6:10   ` CK Hu
2019-07-17 21:48     ` Ryan Case
2019-06-27  8:01 ` [v5 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
2019-06-28  5:57   ` CK Hu
2019-06-27  8:01 ` [v5 3/7] drm/mediatek: add dsi reg commit disable control Jitao Shi
2019-06-27  8:01 ` [v5 4/7] drm/mediatek: add frame size control Jitao Shi
2019-07-01  1:29   ` CK Hu [this message]
2019-06-27  8:01 ` [v5 5/7] drm/mediatek: add mt8183 dsi driver support Jitao Shi
2019-06-27  8:01 ` [v5 6/7] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
2019-07-01  1:43   ` CK Hu
2019-07-17 22:03     ` Ryan Case
2019-06-27  8:01 ` [v5 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi

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