From: Grzegorz Jaszczyk <jaz@semihalf.com>
To: thomas.petazzoni@bootlin.com, lorenzo.pieralisi@arm.com,
bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, mw@semihalf.com,
linux-arm-kernel@lists.infradead.org,
Grzegorz Jaszczyk <jaz@semihalf.com>
Subject: [PATCH v2] PCI: aardvark: fix big endian support
Date: Tue, 16 Jul 2019 14:12:07 +0200 [thread overview]
Message-ID: <1563279127-30678-1-git-send-email-jaz@semihalf.com> (raw)
Initialise every not-byte wide fields of emulated pci bridge config
space with proper cpu_to_le* macro. This is required since the structure
describing config space of emulated bridge assumes little-endian
convention.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
v1->v2
- add missing cpu_to_le32 for class_revison assignment (issues found by
Thomas Petazzoni and also detected by Sparse tool).
drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 134e030..178e92f 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
{
struct pci_bridge_emul *bridge = &pcie->bridge;
- bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
- bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
+ bridge->conf.vendor =
+ cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
+ bridge->conf.device =
+ cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
bridge->conf.class_revision =
- advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
+ cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
/* Support 32 bits I/O addressing */
bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
/* Support 64 bits memory pref */
- bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
- bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
+ bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
+ bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
/* Support interrupt A for MSI feature */
bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
--
2.7.4
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next reply other threads:[~2019-07-16 12:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-16 12:12 Grzegorz Jaszczyk [this message]
2019-09-30 8:17 ` [PATCH v2] PCI: aardvark: fix big endian support Grzegorz Jaszczyk
2019-09-30 14:39 ` Lorenzo Pieralisi
2019-10-04 8:38 ` Grzegorz Jaszczyk
2019-10-17 12:43 ` Lorenzo Pieralisi
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