From: CK Hu <ck.hu@mediatek.com>
To: <yongqiang.niu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4, 22/33] drm/mediatek: add background color input select function for ovl/ovl_2l
Date: Wed, 17 Jul 2019 13:58:29 +0800 [thread overview]
Message-ID: <1563343109.29169.19.camel@mtksdaap41> (raw)
In-Reply-To: <1562625253-29254-23-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Tue, 2019-07-09 at 06:34 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add background color input select function for ovl/ovl_2l
>
> ovl include 4 DRAM layer and 1 background color layer
> ovl_2l include 4 DRAM layer and 1 background color layer
> DRAM layer frame buffer data from render hardware, GPU for example.
> backgournd color layer is embed in ovl/ovl_2l, we can only set
> it color, but not support DRAM frame buffer.
>
> for ovl0->ovl0_2l direct link usecase,
> we need set ovl0_2l background color intput select from ovl0
> if render send DRAM buffer layer number <=4, all these layer read
> by ovl.
> layer0 is at the bottom of all layers.
> layer3 is at the top of all layers.
> if render send DRAM buffer layer numbfer >=4 && <=6
> ovl0 read layer0~3
> ovl0_2l read layer4~5
> layer5 is at the top ot all these layers.
>
> the decision of how to setting ovl0/ovl0_2l read these layer data
> is controlled in mtk crtc, which will be another patch
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index a0ab760..8ca4965 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -27,6 +27,8 @@
> #define DISP_REG_OVL_EN 0x000c
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> +#define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
> @@ -245,6 +247,24 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> mtk_ovl_layer_on(comp, idx);
> }
>
> +static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> +static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
> +{
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_BGCLR_SEL_IN;
> + writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> +}
> +
> static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
> .config = mtk_ovl_config,
> .start = mtk_ovl_start,
> @@ -255,6 +275,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> .layer_on = mtk_ovl_layer_on,
> .layer_off = mtk_ovl_layer_off,
> .layer_config = mtk_ovl_layer_config,
> + .bgclr_in_on = mtk_ovl_bgclr_in_on,
> + .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
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next prev parent reply other threads:[~2019-07-17 5:58 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 22:33 [PATCH v4, 00/33] add drm support for MT8183 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 01/33] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-07-17 3:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 02/33] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-07-24 20:15 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 03/33] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-07-17 3:37 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 04/33] dt-bindings: mediatek: add dither " yongqiang.niu
2019-07-17 3:40 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 05/33] dt-bindings: mediatek: add RDMA1 " yongqiang.niu
2019-07-24 20:16 ` Rob Herring
2019-07-25 3:20 ` CK Hu
2019-07-25 22:23 ` Rob Herring
2019-07-08 22:33 ` [PATCH v4, 06/33] dt-bindings: mediatek: add mutex " yongqiang.niu
2019-07-16 23:59 ` Ryan Case
2019-07-08 22:33 ` [PATCH v4, 07/33] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 08/33] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-07-17 5:22 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 09/33] drm/mediatek: add mutex mod register offset " yongqiang.niu
2019-07-17 5:23 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 10/33] drm/mediatek: add mutex sof " yongqiang.niu
2019-07-17 5:28 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 11/33] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-07-17 5:31 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 12/33] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-07-17 5:35 ` CK Hu
2019-08-29 12:39 ` Yongqiang Niu
2019-07-08 22:33 ` [PATCH v4, 13/33] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-07-17 5:46 ` CK Hu
2019-07-08 22:33 ` [PATCH v4, 14/33] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 15/33] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 16/33] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 17/33] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 18/33] drm/mediatek: add component DITHER yongqiang.niu
2019-07-08 22:33 ` [PATCH v4, 19/33] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 20/33] drm/medaitek: add layer_nr " yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 21/33] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-07-17 5:53 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 22/33] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-07-17 5:58 ` CK Hu [this message]
2019-07-08 22:34 ` [PATCH v4, 23/33] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-07-16 23:13 ` Ryan Case
2019-07-17 6:47 ` CK Hu
2019-08-29 13:15 ` Yongqiang Niu
2019-07-08 22:34 ` [PATCH v4, 24/33] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-07-17 6:55 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 25/33] drm/mediatek: add clock property check before get it yongqiang.niu
2019-07-17 7:01 ` CK Hu
2019-07-08 22:34 ` [PATCH v4, 26/33] drm/mediatek: add connection from OVL0 to OVL_2L0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 27/33] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 28/33] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 29/33] drm/mediatek: add connection from OVL_2L0 to RDMA0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 30/33] drm/mediatek: add connection from OVL_2L1 to RDMA1 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 31/33] drm/mediatek: add connection from DITHER0 to DSI0 yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 32/33] drm/mediatek: add connection from RDMA0 " yongqiang.niu
2019-07-08 22:34 ` [PATCH v4, 33/33] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
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