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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	 Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
	chao.hao@mediatek.com, linux-kernel@vger.kernel.org,
	Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org, yong.wu@mediatek.com,
	ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
	Matthias Kaehlcke <mka@chromium.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 20/23] memory: mtk-smi: Add bus_sel for mt8183
Date: Wed, 21 Aug 2019 21:53:23 +0800
Message-ID: <1566395606-7975-21-git-send-email-yong.wu@mediatek.com> (raw)
In-Reply-To: <1566395606-7975-1-git-send-email-yong.wu@mediatek.com>

There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
mmu0 or mmu1 to balance the bandwidth via the smi-common register
SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).

In mt8183, For better performance, we switch larb1/2/5/7 to enter
mmu1 while the others still keep enter mmu0.

In mt8173 and mt2712, we don't get the performance issue,
Keep its default value(0x0), that means all the larbs enter mmu0.

Note: smi gen1(mt2701/mt7623) don't have this bus_sel.

And, the base of smi-common is completely different with smi_ao_base
of gen1, thus I add new variable for that.

CC: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 drivers/memory/mtk-smi.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 2bb55b86..289e595 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -41,6 +41,12 @@
 #define SMI_LARB_NONSEC_CON(id)	(0x380 + ((id) * 4))
 #define F_MMU_EN		BIT(0)
 
+/* SMI COMMON */
+#define SMI_BUS_SEL			0x220
+#define SMI_BUS_LARB_SHIFT(larbid)	((larbid) << 1)
+/* All are MMU0 defaultly. Only specialize mmu1 here. */
+#define F_MMU1_LARB(larbid)		(0x1 << SMI_BUS_LARB_SHIFT(larbid))
+
 enum mtk_smi_gen {
 	MTK_SMI_GEN1,
 	MTK_SMI_GEN2
@@ -49,6 +55,7 @@ enum mtk_smi_gen {
 struct mtk_smi_common_plat {
 	enum mtk_smi_gen gen;
 	bool             has_gals;
+	u32              bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
 };
 
 struct mtk_smi_larb_gen {
@@ -64,8 +71,10 @@ struct mtk_smi {
 	struct clk			*clk_apb, *clk_smi;
 	struct clk			*clk_gals0, *clk_gals1;
 	struct clk			*clk_async; /*only needed by mt2701*/
-	void __iomem			*smi_ao_base;
-
+	union {
+		void __iomem		*smi_ao_base; /* only for gen1 */
+		void __iomem		*base;	      /* only for gen2 */
+	};
 	const struct mtk_smi_common_plat *plat;
 };
 
@@ -402,6 +411,8 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
 	.gen      = MTK_SMI_GEN2,
 	.has_gals = true,
+	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
+		    F_MMU1_LARB(7),
 };
 
 static const struct of_device_id mtk_smi_common_of_ids[] = {
@@ -474,6 +485,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
 		ret = clk_prepare_enable(common->clk_async);
 		if (ret)
 			return ret;
+	} else {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		common->base = devm_ioremap_resource(dev, res);
+		if (IS_ERR(common->base))
+			return PTR_ERR(common->base);
 	}
 	pm_runtime_enable(dev);
 	platform_set_drvdata(pdev, common);
@@ -489,6 +505,7 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
 {
 	struct mtk_smi *common = dev_get_drvdata(dev);
+	u32 bus_sel = common->plat->bus_sel;
 	int ret;
 
 	ret = mtk_smi_clk_enable(common);
@@ -496,6 +513,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
 		dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
 		return ret;
 	}
+
+	if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
+		writel(bus_sel, common->base + SMI_BUS_SEL);
 	return 0;
 }
 
-- 
1.9.1


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  parent reply index

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-21 13:53 [PATCH v10 00/23] MT8183 IOMMU SUPPORT Yong Wu
2019-08-21 13:53 ` [PATCH v10 01/23] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Yong Wu
2019-08-21 13:53 ` [PATCH v10 02/23] iommu/mediatek: Use a struct as the platform data Yong Wu
2019-08-21 13:53 ` [PATCH v10 03/23] memory: mtk-smi: Use a general config_port interface Yong Wu
2019-08-21 13:53 ` [PATCH v10 04/23] memory: mtk-smi: Use a struct for the platform data for smi-common Yong Wu
2019-08-21 13:53 ` [PATCH v10 05/23] iommu/mediatek: Fix iova_to_phys PA start for 4GB mode Yong Wu
2019-08-21 13:53 ` [PATCH v10 06/23] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers Yong Wu
2019-08-21 13:53 ` [PATCH v10 07/23] iommu/io-pgtable-arm-v7s: Use ias/oas to check the valid iova/pa Yong Wu
2019-08-21 15:25   ` Will Deacon
2019-08-21 13:53 ` [PATCH v10 08/23] iommu/io-pgtable-arm-v7s: Rename the quirk from MTK_4GB to MTK_EXT Yong Wu
2019-08-21 15:25   ` Will Deacon
2019-08-21 13:53 ` [PATCH v10 09/23] iommu/io-pgtable-arm-v7s: Extend to support PA[33:32] for MediaTek Yong Wu
2019-08-21 15:24   ` Will Deacon
2019-08-21 15:34     ` Robin Murphy
2019-08-21 16:35       ` Will Deacon
2019-08-22  8:59       ` Yong Wu
2019-08-22  8:56     ` Yong Wu
2019-08-22 10:08       ` Will Deacon
2019-08-22 10:08       ` Robin Murphy
2019-08-22 10:17         ` Will Deacon
2019-08-22 10:57           ` Robin Murphy
2019-08-22 11:28             ` Will Deacon
2019-08-22 12:05               ` Yong Wu
2019-08-22 17:14                 ` Will Deacon
2019-08-21 13:53 ` [PATCH v10 10/23] iommu/mediatek: Adjust the PA for the 4GB Mode Yong Wu
2019-08-21 13:53 ` [PATCH v10 11/23] iommu/mediatek: Add bclk can be supported optionally Yong Wu
2019-08-21 13:53 ` [PATCH v10 12/23] iommu/mediatek: Add larb-id remapped support Yong Wu
2019-08-21 13:53 ` [PATCH v10 13/23] iommu/mediatek: Refine protect memory definition Yong Wu
2019-08-21 13:53 ` [PATCH v10 14/23] iommu/mediatek: Move reset_axi into plat_data Yong Wu
2019-08-21 13:53 ` [PATCH v10 15/23] iommu/mediatek: Move vld_pa_rng " Yong Wu
2019-08-21 13:53 ` [PATCH v10 16/23] memory: mtk-smi: Add gals support Yong Wu
2019-08-21 13:53 ` [PATCH v10 17/23] iommu/mediatek: Add mt8183 IOMMU support Yong Wu
2019-08-21 13:53 ` [PATCH v10 18/23] iommu/mediatek: Add mmu1 support Yong Wu
2019-08-21 13:53 ` [PATCH v10 19/23] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu
2019-08-21 13:53 ` Yong Wu [this message]
2019-08-21 13:53 ` [PATCH v10 21/23] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu
2019-08-21 13:53 ` [PATCH v10 22/23] memory: mtk-smi: Get rid of need_larbid Yong Wu
2019-08-21 13:53 ` [PATCH v10 23/23] iommu/mediatek: Clean up struct mtk_smi_iommu Yong Wu
2019-08-22 14:07   ` Matthias Brugger

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