From: Peng Fan <peng.fan@nxp.com>
To: "mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
Aisheng Dong <aisheng.dong@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>, Abel Vesa <abel.vesa@nxp.com>,
Anson Huang <anson.huang@nxp.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Jacky Bai <ping.bai@nxp.com>
Subject: [PATCH] clk: imx: lpcg: write twice when writing lpcg regs
Date: Tue, 27 Aug 2019 08:17:50 +0000 [thread overview]
Message-ID: <1566936978-28519-1-git-send-email-peng.fan@nxp.com> (raw)
From: Peng Fan <peng.fan@nxp.com>
There is hardware issue that:
The output clock the LPCG cell will not turn back on as expected,
even though a read of the IPG registers in the LPCG indicates that
the clock should be enabled.
The software workaround is to write twice to enable the LPCG clock
output.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-lpcg-scu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c
index a73a799fb777..7391d0668ec4 100644
--- a/drivers/clk/imx/clk-lpcg-scu.c
+++ b/drivers/clk/imx/clk-lpcg-scu.c
@@ -54,6 +54,11 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw)
reg |= val << clk->bit_idx;
writel(reg, clk->reg);
+ /*
+ * There is hardware bug. When enabling the LPCG clock
+ * output, SW can write the enabling value twice
+ */
+ writel(reg, clk->reg);
spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
@@ -71,6 +76,11 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw)
reg = readl_relaxed(clk->reg);
reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
writel(reg, clk->reg);
+ /*
+ * There is hardware bug. When enabling the LPCG clock
+ * output, SW can write the enabling value twice
+ */
+ writel(reg, clk->reg);
spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
}
--
2.16.4
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next reply other threads:[~2019-08-27 8:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 8:17 Peng Fan [this message]
2019-09-06 17:20 ` [PATCH] clk: imx: lpcg: write twice when writing lpcg regs Stephen Boyd
2019-09-09 11:51 ` Dong Aisheng
2019-09-10 2:47 ` Anson Huang
2019-09-10 11:50 ` Daniel Baluta
2019-09-13 3:42 ` Shawn Guo
2019-09-09 11:44 ` Dong Aisheng
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