From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <linux-arm-kernel@lists.infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>,
Mark Rutland <mark.rutland@arm.com>,
John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
Hanjun Guo <guohanjun@huawei.com>
Subject: [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform
Date: Thu, 7 Nov 2019 15:56:04 +0800 [thread overview]
Message-ID: <1573113364-32531-1-git-send-email-zhangshaokun@hisilicon.com> (raw)
For some HiSilicon platform, the originally designed SCCL_ID and CCL_ID
are not satisfied with much rich topology when the MT is set, so we
extend the SCCL_ID to MPIDR[aff3] and CCL_ID to MPIDR[aff2]. Let's
update this for HiSilicon uncore PMU driver.
Cc: John Garry <john.garry@huawei.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_pmu.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index 79f76f8dda8e..96183e31b96a 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -15,6 +15,7 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
+#include <asm/cputype.h>
#include <asm/local64.h>
#include "hisi_uncore_pmu.h"
@@ -338,8 +339,10 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
/*
* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
- * If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
- * and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
+ * If multi-threading is supported, On Huawei Kunpeng 920 SoC whose cpu
+ * core is tsv110, CCL_ID is the low 3-bits in MPIDR[Aff2] and SCCL_ID
+ * is the upper 5-bits of Aff2 field; while for other cpu types, SCCL_ID
+ * is in MPIDR[Aff3] and CCL_ID is in MPIDR[Aff2], if not, SCCL_ID
* is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
*/
static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
@@ -347,12 +350,19 @@ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
u64 mpidr = read_cpuid_mpidr();
if (mpidr & MPIDR_MT_BITMASK) {
- int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
-
- if (sccl_id)
- *sccl_id = aff2 >> 3;
- if (ccl_id)
- *ccl_id = aff2 & 0x7;
+ if (read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
+ int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+
+ if (sccl_id)
+ *sccl_id = aff2 >> 3;
+ if (ccl_id)
+ *ccl_id = aff2 & 0x7;
+ } else {
+ if (sccl_id)
+ *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+ if (ccl_id)
+ *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+ }
} else {
if (sccl_id)
*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
--
2.7.4
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next reply other threads:[~2019-11-07 7:56 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-07 7:56 Shaokun Zhang [this message]
2019-11-07 11:31 ` [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform Mark Rutland
2019-11-07 11:40 ` Will Deacon
2019-11-07 11:50 ` John Garry
2019-11-07 11:56 ` Mark Rutland
2019-11-07 12:06 ` John Garry
2019-11-07 12:11 ` Mark Rutland
2019-11-07 13:04 ` John Garry
2019-11-07 13:09 ` Will Deacon
2019-11-08 1:25 ` Shaokun Zhang
2019-11-08 9:49 ` Will Deacon
2019-11-09 2:51 ` [PATCH] drivers/perf: hisi: Simplify hisi_read_sccl_and_ccl_id and its comment Shaokun Zhang
2019-11-11 13:49 ` John Garry
2019-11-12 0:50 ` Shaokun Zhang
2019-11-08 1:18 ` [PATCH] drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform Shaokun Zhang
2019-11-08 1:15 ` Shaokun Zhang
2019-11-08 1:28 ` Shaokun Zhang
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