From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
David Airlie <airlied@linux.ie>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v6 02/17] arm64: dts: add display nodes for mt8183
Date: Fri, 3 Jan 2020 11:12:13 +0800 [thread overview]
Message-ID: <1578021148-32413-3-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1578021148-32413-1-git-send-email-yongqiang.niu@mediatek.com>
This patch add display nodes for mt8183
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 91217e4f..28beb1d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -30,6 +30,11 @@
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
+ ovl0 = &ovl0;
+ ovl_2l0 = &ovl_2l0;
+ ovl_2l1 = &ovl_2l1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
};
cpus {
@@ -648,9 +653,102 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
};
+ ovl0: ovl@14008000 {
+ compatible = "mediatek,mt8183-disp-ovl";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ };
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ };
+
+ ovl_2l1: ovl@1400a000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+ };
+
+ rdma0: rdma@1400b000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ mediatek,rdma_fifo_size = <5120>;
+ };
+
+ rdma1: rdma@1400c000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ mediatek,rdma_fifo_size = <2048>;
+ };
+
+ color0: color@1400e000 {
+ compatible = "mediatek,mt8183-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@14010000 {
+ compatible = "mediatek,mt8183-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@14011000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ mutex: mutex@14016000 {
+ compatible = "mediatek,mt8183-disp-mutex";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ };
+
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2020-01-03 3:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 3:12 [RESEND PATCH v6 00/17] add drm support for MT8183 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 01/17] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Yongqiang Niu
2020-01-03 5:10 ` CK Hu
2020-01-03 22:26 ` Rob Herring
2020-01-03 3:12 ` Yongqiang Niu [this message]
2020-01-03 3:12 ` [RESEND PATCH v6 03/17] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in Yongqiang Niu
2020-01-03 5:36 ` CK Hu
2020-01-03 3:12 ` [RESEND PATCH v6 04/17] drm/mediatek: make sout select function format same with select input Yongqiang Niu
2020-01-03 5:44 ` CK Hu
2020-01-03 3:12 ` [RESEND PATCH v6 05/17] drm/mediatek: add mmsys private data for ddp path config Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 06/17] drm/mediatek: add private data for rdma1 to dpi0 connection Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 07/17] drm/mediatek: add private data for rdma1 to dsi0 connection Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 08/17] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 09/17] drm/mediatek: add connection from OVL0 to OVL_2L0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 10/17] drm/mediatek: add connection from RDMA0 to COLOR0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 11/17] drm/mediatek: add connection from RDMA1 to DSI0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 12/17] drm/mediatek: add connection from OVL_2L0 to RDMA0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 13/17] drm/mediatek: add connection from OVL_2L1 to RDMA1 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 14/17] drm/mediatek: add connection from DITHER0 to DSI0 Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 15/17] drm/mediatek: add connection from RDMA0 " Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 16/17] drm/mediatek: add fifo_size into rdma private data Yongqiang Niu
2020-01-03 3:12 ` [RESEND PATCH v6 17/17] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu
2020-01-03 4:58 ` [RESEND PATCH v6 00/17] add drm support for MT8183 CK Hu
2020-03-26 14:57 ` CK Hu
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