* [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP @ 2020-01-15 1:39 Anson Huang 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang ` (2 more replies) 0 siblings, 3 replies; 11+ messages in thread From: Anson Huang @ 2020-01-15 1:39 UTC (permalink / raw) To: aisheng.dong, festevam, shawnguo, stefan, kernel, linus.walleij, robh+dt, mark.rutland, s.hauer, catalin.marinas, will, abel.vesa, bjorn.andersson, olof, maxime, leonard.crestez, dinguyen, marcin.juszkiewicz, linux-gpio, devicetree, linux-arm-kernel, linux-kernel Cc: Linux-imx Add binding doc for i.MX8MP pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> --- Changes since V8: - the lisence should be GPL-2.0 --- .../bindings/pinctrl/fsl,imx8mp-pinctrl.yaml | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml new file mode 100644 index 0000000..2e31e12 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8MP IOMUX Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8mp-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = < + 0x228 0x488 0x5F0 0x0 0x6 0x49 + 0x228 0x488 0x000 0x0 0x0 0x49 + >; + }; + }; + +... -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support 2020-01-15 1:39 [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Anson Huang @ 2020-01-15 1:39 ` Anson Huang 2020-01-15 13:23 ` Linus Walleij ` (2 more replies) 2020-01-15 1:39 ` [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Anson Huang 2020-01-23 14:48 ` [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Linus Walleij 2 siblings, 3 replies; 11+ messages in thread From: Anson Huang @ 2020-01-15 1:39 UTC (permalink / raw) To: aisheng.dong, festevam, shawnguo, stefan, kernel, linus.walleij, robh+dt, mark.rutland, s.hauer, catalin.marinas, will, abel.vesa, bjorn.andersson, olof, maxime, leonard.crestez, dinguyen, marcin.juszkiewicz, linux-gpio, devicetree, linux-arm-kernel, linux-kernel Cc: Linux-imx Add the pinctrl driver support for i.MX8MP. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> --- No change. --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8mp.c | 345 +++++++++++++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mp.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 3ea9ce3..de775a8 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -137,6 +137,13 @@ config PINCTRL_IMX8MN help Say Y here to enable the imx8mn pinctrl driver +config PINCTRL_IMX8MP + bool "IMX8MP pinctrl driver" + depends on ARCH_MXC && ARM64 + select PINCTRL_IMX + help + Say Y here to enable the imx8mp pinctrl driver + config PINCTRL_IMX8MQ bool "IMX8MQ pinctrl driver" depends on ARCH_MXC && ARM64 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 78e9140..0ebd3af 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o +obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mp.c b/drivers/pinctrl/freescale/pinctrl-imx8mp.c new file mode 100644 index 0000000..e3f644c --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8mp.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-imx.h" + +enum imx8mp_pads { + MX8MP_IOMUXC_RESERVE0 = 0, + MX8MP_IOMUXC_RESERVE1 = 1, + MX8MP_IOMUXC_RESERVE2 = 2, + MX8MP_IOMUXC_RESERVE3 = 3, + MX8MP_IOMUXC_RESERVE4 = 4, + MX8MP_IOMUXC_GPIO1_IO00 = 5, + MX8MP_IOMUXC_GPIO1_IO01 = 6, + MX8MP_IOMUXC_GPIO1_IO02 = 7, + MX8MP_IOMUXC_GPIO1_IO03 = 8, + MX8MP_IOMUXC_GPIO1_IO04 = 9, + MX8MP_IOMUXC_GPIO1_IO05 = 10, + MX8MP_IOMUXC_GPIO1_IO06 = 11, + MX8MP_IOMUXC_GPIO1_IO07 = 12, + MX8MP_IOMUXC_GPIO1_IO08 = 13, + MX8MP_IOMUXC_GPIO1_IO09 = 14, + MX8MP_IOMUXC_GPIO1_IO10 = 15, + MX8MP_IOMUXC_GPIO1_IO11 = 16, + MX8MP_IOMUXC_GPIO1_IO12 = 17, + MX8MP_IOMUXC_GPIO1_IO13 = 18, + MX8MP_IOMUXC_GPIO1_IO14 = 19, + MX8MP_IOMUXC_GPIO1_IO15 = 20, + MX8MP_IOMUXC_ENET_MDC = 21, + MX8MP_IOMUXC_ENET_MDIO = 22, + MX8MP_IOMUXC_ENET_TD3 = 23, + MX8MP_IOMUXC_ENET_TD2 = 24, + MX8MP_IOMUXC_ENET_TD1 = 25, + MX8MP_IOMUXC_ENET_TD0 = 26, + MX8MP_IOMUXC_ENET_TX_CTL = 27, + MX8MP_IOMUXC_ENET_TXC = 28, + MX8MP_IOMUXC_ENET_RX_CTL = 29, + MX8MP_IOMUXC_ENET_RXC = 30, + MX8MP_IOMUXC_ENET_RD0 = 31, + MX8MP_IOMUXC_ENET_RD1 = 32, + MX8MP_IOMUXC_ENET_RD2 = 33, + MX8MP_IOMUXC_ENET_RD3 = 34, + MX8MP_IOMUXC_SD1_CLK = 35, + MX8MP_IOMUXC_SD1_CMD = 36, + MX8MP_IOMUXC_SD1_DATA0 = 37, + MX8MP_IOMUXC_SD1_DATA1 = 38, + MX8MP_IOMUXC_SD1_DATA2 = 39, + MX8MP_IOMUXC_SD1_DATA3 = 40, + MX8MP_IOMUXC_SD1_DATA4 = 41, + MX8MP_IOMUXC_SD1_DATA5 = 42, + MX8MP_IOMUXC_SD1_DATA6 = 43, + MX8MP_IOMUXC_SD1_DATA7 = 44, + MX8MP_IOMUXC_SD1_RESET_B = 45, + MX8MP_IOMUXC_SD1_STROBE = 46, + MX8MP_IOMUXC_SD2_CD_B = 47, + MX8MP_IOMUXC_SD2_CLK = 48, + MX8MP_IOMUXC_SD2_CMD = 49, + MX8MP_IOMUXC_SD2_DATA0 = 50, + MX8MP_IOMUXC_SD2_DATA1 = 51, + MX8MP_IOMUXC_SD2_DATA2 = 52, + MX8MP_IOMUXC_SD2_DATA3 = 53, + MX8MP_IOMUXC_SD2_RESET_B = 54, + MX8MP_IOMUXC_SD2_WP = 55, + MX8MP_IOMUXC_NAND_ALE = 56, + MX8MP_IOMUXC_NAND_CE0_B = 57, + MX8MP_IOMUXC_NAND_CE1_B = 58, + MX8MP_IOMUXC_NAND_CE2_B = 59, + MX8MP_IOMUXC_NAND_CE3_B = 60, + MX8MP_IOMUXC_NAND_CLE = 61, + MX8MP_IOMUXC_NAND_DATA00 = 62, + MX8MP_IOMUXC_NAND_DATA01 = 63, + MX8MP_IOMUXC_NAND_DATA02 = 64, + MX8MP_IOMUXC_NAND_DATA03 = 65, + MX8MP_IOMUXC_NAND_DATA04 = 66, + MX8MP_IOMUXC_NAND_DATA05 = 67, + MX8MP_IOMUXC_NAND_DATA06 = 68, + MX8MP_IOMUXC_NAND_DATA07 = 69, + MX8MP_IOMUXC_NAND_DQS = 70, + MX8MP_IOMUXC_NAND_RE_B = 71, + MX8MP_IOMUXC_NAND_READY_B = 72, + MX8MP_IOMUXC_NAND_WE_B = 73, + MX8MP_IOMUXC_NAND_WP_B = 74, + MX8MP_IOMUXC_SAI5_RXFS = 75, + MX8MP_IOMUXC_SAI5_RXC = 76, + MX8MP_IOMUXC_SAI5_RXD0 = 77, + MX8MP_IOMUXC_SAI5_RXD1 = 78, + MX8MP_IOMUXC_SAI5_RXD2 = 79, + MX8MP_IOMUXC_SAI5_RXD3 = 80, + MX8MP_IOMUXC_SAI5_MCLK = 81, + MX8MP_IOMUXC_SAI1_RXFS = 82, + MX8MP_IOMUXC_SAI1_RXC = 83, + MX8MP_IOMUXC_SAI1_RXD0 = 84, + MX8MP_IOMUXC_SAI1_RXD1 = 85, + MX8MP_IOMUXC_SAI1_RXD2 = 86, + MX8MP_IOMUXC_SAI1_RXD3 = 87, + MX8MP_IOMUXC_SAI1_RXD4 = 88, + MX8MP_IOMUXC_SAI1_RXD5 = 89, + MX8MP_IOMUXC_SAI1_RXD6 = 90, + MX8MP_IOMUXC_SAI1_RXD7 = 91, + MX8MP_IOMUXC_SAI1_TXFS = 92, + MX8MP_IOMUXC_SAI1_TXC = 93, + MX8MP_IOMUXC_SAI1_TXD0 = 94, + MX8MP_IOMUXC_SAI1_TXD1 = 95, + MX8MP_IOMUXC_SAI1_TXD2 = 96, + MX8MP_IOMUXC_SAI1_TXD3 = 97, + MX8MP_IOMUXC_SAI1_TXD4 = 98, + MX8MP_IOMUXC_SAI1_TXD5 = 99, + MX8MP_IOMUXC_SAI1_TXD6 = 100, + MX8MP_IOMUXC_SAI1_TXD7 = 101, + MX8MP_IOMUXC_SAI1_MCLK = 102, + MX8MP_IOMUXC_SAI2_RXFS = 103, + MX8MP_IOMUXC_SAI2_RXC = 104, + MX8MP_IOMUXC_SAI2_RXD0 = 105, + MX8MP_IOMUXC_SAI2_TXFS = 106, + MX8MP_IOMUXC_SAI2_TXC = 107, + MX8MP_IOMUXC_SAI2_TXD0 = 108, + MX8MP_IOMUXC_SAI2_MCLK = 109, + MX8MP_IOMUXC_SAI3_RXFS = 110, + MX8MP_IOMUXC_SAI3_RXC = 111, + MX8MP_IOMUXC_SAI3_RXD = 112, + MX8MP_IOMUXC_SAI3_TXFS = 113, + MX8MP_IOMUXC_SAI3_TXC = 114, + MX8MP_IOMUXC_SAI3_TXD = 115, + MX8MP_IOMUXC_SAI3_MCLK = 116, + MX8MP_IOMUXC_SPDIF_TX = 117, + MX8MP_IOMUXC_SPDIF_RX = 118, + MX8MP_IOMUXC_SPDIF_EXT_CLK = 119, + MX8MP_IOMUXC_ECSPI1_SCLK = 120, + MX8MP_IOMUXC_ECSPI1_MOSI = 121, + MX8MP_IOMUXC_ECSPI1_MISO = 122, + MX8MP_IOMUXC_ECSPI1_SS0 = 123, + MX8MP_IOMUXC_ECSPI2_SCLK = 124, + MX8MP_IOMUXC_ECSPI2_MOSI = 125, + MX8MP_IOMUXC_ECSPI2_MISO = 126, + MX8MP_IOMUXC_ECSPI2_SS0 = 127, + MX8MP_IOMUXC_I2C1_SCL = 128, + MX8MP_IOMUXC_I2C1_SDA = 129, + MX8MP_IOMUXC_I2C2_SCL = 130, + MX8MP_IOMUXC_I2C2_SDA = 131, + MX8MP_IOMUXC_I2C3_SCL = 132, + MX8MP_IOMUXC_I2C3_SDA = 133, + MX8MP_IOMUXC_I2C4_SCL = 134, + MX8MP_IOMUXC_I2C4_SDA = 135, + MX8MP_IOMUXC_UART1_RXD = 136, + MX8MP_IOMUXC_UART1_TXD = 137, + MX8MP_IOMUXC_UART2_RXD = 138, + MX8MP_IOMUXC_UART2_TXD = 139, + MX8MP_IOMUXC_UART3_RXD = 140, + MX8MP_IOMUXC_UART3_TXD = 141, + MX8MP_IOMUXC_UART4_RXD = 142, + MX8MP_IOMUXC_UART4_TXD = 143, + MX8MP_IOMUXC_HDMI_DDC_SCL = 144, + MX8MP_IOMUXC_HDMI_DDC_SDA = 145, + MX8MP_IOMUXC_HDMI_CEC = 146, + MX8MP_IOMUXC_HDMI_HPD = 147, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC), + IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD), +}; + +static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = { + .pins = imx8mp_pinctrl_pads, + .npins = ARRAY_SIZE(imx8mp_pinctrl_pads), + .gpr_compatible = "fsl,imx8mp-iomuxc-gpr", +}; + +static const struct of_device_id imx8mp_pinctrl_of_match[] = { + { .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imx8mp_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info); +} + +static struct platform_driver imx8mp_pinctrl_driver = { + .driver = { + .name = "imx8mp-pinctrl", + .of_match_table = of_match_ptr(imx8mp_pinctrl_of_match), + }, + .probe = imx8mp_pinctrl_probe, +}; + +static int __init imx8mp_pinctrl_init(void) +{ + return platform_driver_register(&imx8mp_pinctrl_driver); +} +arch_initcall(imx8mp_pinctrl_init); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang @ 2020-01-15 13:23 ` Linus Walleij 2020-01-16 1:33 ` Anson Huang 2020-01-15 15:44 ` Fabio Estevam 2020-01-23 14:50 ` Linus Walleij 2 siblings, 1 reply; 11+ messages in thread From: Linus Walleij @ 2020-01-15 13:23 UTC (permalink / raw) To: Anson Huang Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Dong Aisheng, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo Hi Anson, On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> wrote: > > Add the pinctrl driver support for i.MX8MP. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > No change. Can this patch be applied independently of the rest of the patches? In that case I am just waiting for a review from one of the Freescale pin control maintainers then I can merge this. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support 2020-01-15 13:23 ` Linus Walleij @ 2020-01-16 1:33 ` Anson Huang 0 siblings, 0 replies; 11+ messages in thread From: Anson Huang @ 2020-01-16 1:33 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, dl-linux-imx, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Aisheng Dong, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo Hi, Linus > Subject: Re: [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver > support > > Hi Anson, > > On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> > wrote: > > > > Add the pinctrl driver support for i.MX8MP. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > > --- > > No change. > > Can this patch be applied independently of the rest of the patches? I think so. Thanks, Anson _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang 2020-01-15 13:23 ` Linus Walleij @ 2020-01-15 15:44 ` Fabio Estevam 2020-01-23 14:50 ` Linus Walleij 2 siblings, 0 replies; 11+ messages in thread From: Fabio Estevam @ 2020-01-15 15:44 UTC (permalink / raw) To: Anson Huang Cc: Mark Rutland, Catalin Marinas, Linus Walleij, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, marcin.juszkiewicz, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Dong Aisheng, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo On Tue, Jan 14, 2020 at 10:43 PM Anson Huang <Anson.Huang@nxp.com> wrote: > > Add the pinctrl driver support for i.MX8MP. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang 2020-01-15 13:23 ` Linus Walleij 2020-01-15 15:44 ` Fabio Estevam @ 2020-01-23 14:50 ` Linus Walleij 2 siblings, 0 replies; 11+ messages in thread From: Linus Walleij @ 2020-01-23 14:50 UTC (permalink / raw) To: Anson Huang Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Dong Aisheng, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> wrote: > Add the pinctrl driver support for i.MX8MP. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Patch applied with Fabio's review tag. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default 2020-01-15 1:39 [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Anson Huang 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang @ 2020-01-15 1:39 ` Anson Huang 2020-01-23 14:51 ` Linus Walleij 2020-02-12 7:47 ` Shawn Guo 2020-01-23 14:48 ` [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Linus Walleij 2 siblings, 2 replies; 11+ messages in thread From: Anson Huang @ 2020-01-15 1:39 UTC (permalink / raw) To: aisheng.dong, festevam, shawnguo, stefan, kernel, linus.walleij, robh+dt, mark.rutland, s.hauer, catalin.marinas, will, abel.vesa, bjorn.andersson, olof, maxime, leonard.crestez, dinguyen, marcin.juszkiewicz, linux-gpio, devicetree, linux-arm-kernel, linux-kernel Cc: Linux-imx Enable CONFIG_PINCTRL_IMX8MP by default to support i.MX8MP pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> --- No change --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d0ea0d0..d35b417 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -396,6 +396,7 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MM=y CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default 2020-01-15 1:39 ` [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Anson Huang @ 2020-01-23 14:51 ` Linus Walleij 2020-02-10 3:48 ` Anson Huang 2020-02-12 7:47 ` Shawn Guo 1 sibling, 1 reply; 11+ messages in thread From: Linus Walleij @ 2020-01-23 14:51 UTC (permalink / raw) To: Anson Huang Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Dong Aisheng, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> wrote: > Enable CONFIG_PINCTRL_IMX8MP by default to support i.MX8MP > pinctrl driver. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Please merge this one patch through the ARM SoC tree. If don't know who collects the Freescale/iMX patches for ARM SoC right now.... Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default 2020-01-23 14:51 ` Linus Walleij @ 2020-02-10 3:48 ` Anson Huang 0 siblings, 0 replies; 11+ messages in thread From: Anson Huang @ 2020-02-10 3:48 UTC (permalink / raw) To: Linus Walleij Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, dl-linux-imx, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Aisheng Dong, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo Hi, Shawn > Subject: Re: [PATCH V9 3/3] arm64: defconfig: Select > CONFIG_PINCTRL_IMX8MP by default > > On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> > wrote: > > > Enable CONFIG_PINCTRL_IMX8MP by default to support i.MX8MP pinctrl > > driver. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > Please merge this one patch through the ARM SoC tree. > If don't know who collects the Freescale/iMX patches for ARM SoC right > now.... Hi, Shawn Will you pick this patch? Thanks, Anson _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default 2020-01-15 1:39 ` [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Anson Huang 2020-01-23 14:51 ` Linus Walleij @ 2020-02-12 7:47 ` Shawn Guo 1 sibling, 0 replies; 11+ messages in thread From: Shawn Guo @ 2020-02-12 7:47 UTC (permalink / raw) To: Anson Huang Cc: mark.rutland, catalin.marinas, linus.walleij, stefan, bjorn.andersson, leonard.crestez, will, abel.vesa, festevam, marcin.juszkiewicz, Linux-imx, devicetree, s.hauer, linux-gpio, robh+dt, maxime, linux-arm-kernel, aisheng.dong, linux-kernel, dinguyen, kernel, olof On Wed, Jan 15, 2020 at 09:39:08AM +0800, Anson Huang wrote: > Enable CONFIG_PINCTRL_IMX8MP by default to support i.MX8MP > pinctrl driver. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Applied, thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP 2020-01-15 1:39 [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Anson Huang 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang 2020-01-15 1:39 ` [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Anson Huang @ 2020-01-23 14:48 ` Linus Walleij 2 siblings, 0 replies; 11+ messages in thread From: Linus Walleij @ 2020-01-23 14:48 UTC (permalink / raw) To: Anson Huang Cc: Mark Rutland, Catalin Marinas, Stefan Agner, Bjorn Andersson, Leonard Crestez, Will Deacon, Abel Vesa, Fabio Estevam, Marcin Juszkiewicz, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, open list:GPIO SUBSYSTEM, Rob Herring, maxime, Linux ARM, Dong Aisheng, linux-kernel, Dinh Nguyen, Sascha Hauer, Olof Johansson, Shawn Guo On Wed, Jan 15, 2020 at 2:43 AM Anson Huang <Anson.Huang@nxp.com> wrote: > Add binding doc for i.MX8MP pinctrl driver. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > Changes since V8: > - the lisence should be GPL-2.0 Patch applied. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-12 7:47 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-15 1:39 [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Anson Huang 2020-01-15 1:39 ` [PATCH V9 2/3] pinctrl: freescale: Add i.MX8MP pinctrl driver support Anson Huang 2020-01-15 13:23 ` Linus Walleij 2020-01-16 1:33 ` Anson Huang 2020-01-15 15:44 ` Fabio Estevam 2020-01-23 14:50 ` Linus Walleij 2020-01-15 1:39 ` [PATCH V9 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MP by default Anson Huang 2020-01-23 14:51 ` Linus Walleij 2020-02-10 3:48 ` Anson Huang 2020-02-12 7:47 ` Shawn Guo 2020-01-23 14:48 ` [PATCH V9 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Linus Walleij
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