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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Will Deacon <will@kernel.org>,
	linux-kernel@vger.kernel.org,
	Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register
Date: Tue, 28 Jan 2020 18:09:05 +0530	[thread overview]
Message-ID: <1580215149-21492-3-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com>

Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487E.a
specification. Except RAS and AMU, all other feature bits are now enabled.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 3 +++
 arch/arm64/kernel/cpufeature.c  | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 054aab7ebf1b..469d61c8fabf 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -718,6 +718,9 @@
 #define ID_ISAR6_DP_SHIFT		4
 #define ID_ISAR6_JSCVT_SHIFT		0
 
+#define ID_PFR0_DIT_SHIFT		24
+#define ID_PFR0_CSV2_SHIFT		16
+
 #define ID_PFR2_SSBS_SHIFT		4
 #define ID_PFR2_CSV3_SHIFT		0
 
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c1e837fc8f97..9e4dab15c608 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -341,6 +341,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),		/* State3 */
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),		/* State2 */
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),		/* State1 */
-- 
2.20.1


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  parent reply	other threads:[~2020-01-28 12:40 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-03-20 18:03   ` Suzuki K Poulose
2020-04-09 12:54   ` Will Deacon
2020-04-13  3:32     ` Anshuman Khandual
2020-01-28 12:39 ` Anshuman Khandual [this message]
2020-03-20 18:07   ` [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register Suzuki K Poulose
2020-04-02  2:38     ` Anshuman Khandual
2020-04-09 12:55   ` Will Deacon
2020-04-13  3:35     ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 3/6] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-03-20 18:11   ` Suzuki K Poulose
2020-04-02  2:38     ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 4/6] arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-03-20 18:16   ` Suzuki K Poulose
2020-01-28 12:39 ` [PATCH 5/6] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-03-20 18:19   ` Suzuki K Poulose
2020-04-02  3:00     ` Anshuman Khandual
2020-04-09 12:53     ` Will Deacon
2020-04-13  3:39       ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-03-20 18:40   ` Suzuki K Poulose
2020-04-02  2:44     ` Anshuman Khandual
2020-02-14  4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-02-14 15:58   ` Peter Maydell
2020-04-02  2:33     ` Anshuman Khandual
2020-03-20 18:49   ` Suzuki K Poulose
2020-04-06 17:09 ` Will Deacon
2020-04-07  8:50   ` Anshuman Khandual
2020-04-09 13:54     ` Will Deacon

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