From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>,
Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>
Subject: [PATCH 5/6] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register
Date: Tue, 28 Jan 2020 18:09:08 +0530 [thread overview]
Message-ID: <1580215149-21492-6-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com>
ID_DFR0 based TraceFilt feature should not be exposed. Hence lets drop it.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/kernel/cpufeature.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2726bd6441da..a8ded1f0eeaf 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -374,7 +374,6 @@ static const struct arm64_ftr_bits ftr_id_pfr2[] = {
};
static const struct arm64_ftr_bits ftr_id_dfr0[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
--
2.20.1
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next prev parent reply other threads:[~2020-01-28 12:41 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 12:39 [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-01-28 12:39 ` [PATCH 1/6] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-03-20 18:03 ` Suzuki K Poulose
2020-04-09 12:54 ` Will Deacon
2020-04-13 3:32 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 2/6] arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register Anshuman Khandual
2020-03-20 18:07 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-04-09 12:55 ` Will Deacon
2020-04-13 3:35 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 3/6] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-03-20 18:11 ` Suzuki K Poulose
2020-04-02 2:38 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 4/6] arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-03-20 18:16 ` Suzuki K Poulose
2020-01-28 12:39 ` Anshuman Khandual [this message]
2020-03-20 18:19 ` [PATCH 5/6] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Suzuki K Poulose
2020-04-02 3:00 ` Anshuman Khandual
2020-04-09 12:53 ` Will Deacon
2020-04-13 3:39 ` Anshuman Khandual
2020-01-28 12:39 ` [PATCH 6/6] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-03-20 18:40 ` Suzuki K Poulose
2020-04-02 2:44 ` Anshuman Khandual
2020-02-14 4:23 ` [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Anshuman Khandual
2020-02-14 15:58 ` Peter Maydell
2020-04-02 2:33 ` Anshuman Khandual
2020-03-20 18:49 ` Suzuki K Poulose
2020-04-06 17:09 ` Will Deacon
2020-04-07 8:50 ` Anshuman Khandual
2020-04-09 13:54 ` Will Deacon
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