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From: dillon.minfei@gmail.com
To: robh+dt@kernel.org, p.zabel@pengutronix.de,
	mcoquelin.stm32@gmail.com, alexandre.torgue@st.com,
	thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie,
	daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org,
	andy.shevchenko@gmail.com, noralf@tronnes.org,
	linus.walleij@linaro.org, broonie@kernel.org
Cc: devicetree@vger.kernel.org, dillonhua@gmail.com,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org,
	dillon min <dillon.minfei@gmail.com>,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate
Date: Wed, 27 May 2020 15:27:29 +0800	[thread overview]
Message-ID: <1590564453-24499-6-git-send-email-dillon.minfei@gmail.com> (raw)
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>

From: dillon min <dillon.minfei@gmail.com>

This is due to misuse ‘PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
include/dt-bindings/clock/stm32fx-clock.h).

'post_div' point to 'post_div_data[]', 'post_div->pll_num'
is PLL_I2S or PLL_SAI.

'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
from stm32f4_rcc_register_pll() but, at line 1777 of
driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
equal to 'clks[PLL_SAI]', this is invalid array member at that time.

Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---

Hi Stephen Boyd,

This update include below changes since V5
1 separate '[PATCH v5 5/8]' patch to two submits
2 each one has a Fixes tags

best regards.

 drivers/clk/clk-stm32f4.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 18117ce5ff85..42ca2dd86aea 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = {
 
 #define MAX_POST_DIV 3
 static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
-	{ CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
+	{ CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
 		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
 
-	{ CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
+	{ CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
 		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
 
-	{ NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
+	{ NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
 		STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
 };
 
-- 
2.7.4


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  parent reply	other threads:[~2020-05-27  7:29 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-27  7:27 [PATCH v6 0/9] Enable ili9341 and l3gd20 on stm32f429-disco dillon.minfei
2020-05-27  7:27 ` [PATCH v6 1/9] ARM: dts: stm32: Add dma config for spi5 dillon.minfei
2020-05-27  7:27 ` [PATCH v6 2/9] ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board dillon.minfei
2020-06-15  9:45   ` Alexandre Torgue
2020-06-15 10:05     ` dillon min
2020-05-27  7:27 ` [PATCH v6 3/9] ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board dillon.minfei
2020-05-27  7:27 ` [PATCH v6 4/9] dt-bindings: display: panel: Add ilitek ili9341 panel bindings dillon.minfei
2020-05-29 16:17   ` Rob Herring
2020-05-27  7:27 ` dillon.minfei [this message]
2020-05-27  8:35   ` [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate Stephen Boyd
2021-03-10 11:43     ` dillon min
2020-05-27  7:27 ` [PATCH v6 6/9] clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after kernel startup dillon.minfei
2020-05-27  8:35   ` Stephen Boyd
2021-03-10 11:43     ` dillon min
2020-05-27  7:27 ` [PATCH v6 7/9] drm/panel: Add ilitek ili9341 panel driver dillon.minfei
2020-05-27  7:27 ` [PATCH v6 8/9] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4 dillon.minfei
2020-05-27  9:51   ` Mark Brown
2020-05-27 10:45     ` dillon min
2020-05-27 11:18       ` Mark Brown
2020-05-27  7:27 ` [PATCH v6 9/9] spi: flags 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' can't be coexit with 'SPI_3WIRE' mode dillon.minfei
2020-06-15  8:49 ` [PATCH v6 0/9] Enable ili9341 and l3gd20 on stm32f429-disco Alexandre Torgue

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