From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Enric Balletbo Serra <eballetbo@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
"Rob Herring" <robh@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org,
Wendell Lin <wendell.lin@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v16 07/11] soc: mediatek: Add extra sram control
Date: Wed, 17 Jun 2020 15:05:13 +0800 [thread overview]
Message-ID: <1592377517-14817-8-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com>
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do
the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index a567346..360d559 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -25,6 +25,7 @@
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
+#define MTK_SCPD_SRAM_ISO BIT(2)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -56,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -290,6 +293,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -299,8 +310,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
- val = readl(ctl_addr);
- val |= scpd->data->sram_pdn_bits;
+ if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) {
+ val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
+ val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
/* Either wait until SRAM_PDN_ACK all 1 or 0 */
--
1.8.1.1.dirty
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next prev parent reply other threads:[~2020-06-17 7:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 7:05 [PATCH v16 00/11] Mediatek MT8183 scpsys support Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 01/11] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 02/11] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 03/11] soc: mediatek: Add basic_clk_name to scp_power_data Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 04/11] soc: mediatek: Remove infracfg misc driver support Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 05/11] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 06/11] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2020-06-17 7:05 ` Weiyi Lu [this message]
2020-06-17 7:05 ` [PATCH v16 08/11] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 09/11] soc: mediatek: Add a comma at the end Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 10/11] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2020-06-17 7:05 ` [PATCH v16 11/11] arm64: dts: Add power-domains property to mfgcfg Weiyi Lu
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