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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id q22sm3643270lfc.33.2020.07.28.02.19.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jul 2020 02:19:34 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Subject: [PATCH v4 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver Date: Tue, 28 Jul 2020 11:18:33 +0200 Message-Id: <1595927918-19845-1-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200728_051938_589090_8A45F8AF X-CRM114-Status: GOOD ( 17.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, david@lechnology.com, praneeth@ti.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, wmills@ti.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi All, The following is a v4 version of the series [1][2][3] that adds an IRQChip driver for the local interrupt controller present within a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs. Please see the v1 cover-letter [1] for details about the features of this interrupt controller. More details can be found in any of the supported SoC TRMs. Eg: Chapter 30.1.6 of AM5728 TRM [4] Please see the individual patches for exact changes in each patch, following are the main changes from v3: - Change interrupt-cells to 3 in order to provide 2-level mapping description in DT for interrupts routed to the main CPU as Marc requested (patch #1 and patch #2). - Get rid of the two distinct code paths in the xlate function and allow to proceed only with 3 parameters description as Marc suggested (patch #2). - Due to above modification squash patch #6 of previous patchset into patch #2. - Merge the irqs-reserved and irqs-shared to one property (patch #1 and #2). [1] https://patchwork.kernel.org/cover/11034561/ [2] https://patchwork.kernel.org/cover/11069749/ [3] https://patchwork.kernel.org/cover/11639055/ [4] http://www.ti.com/lit/pdf/spruhz6 Best regards Grzegorz David Lechner (1): irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk (1): irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Suman Anna (3): dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings irqchip/irq-pruss-intc: Add logic for handling reserved interrupts irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 659 +++++++++++++++++++++ 4 files changed, 827 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml create mode 100644 drivers/irqchip/irq-pruss-intc.c -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel