From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Enric Balletbo Serra <eballetbo@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
James Liao <jamesjj.liao@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Wendell Lin <wendell.lin@mediatek.com>,
linux-clk@vger.kernel.org,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192
Date: Tue, 11 Aug 2020 15:01:54 +0800 [thread overview]
Message-ID: <1597129314.20627.25.camel@mtksdaap41> (raw)
In-Reply-To: <CAFqH_50+_Bt97roTACRhoq8XkfSc1UcHyQP3OCacQR5oK-viOg@mail.gmail.com>
On Wed, 2020-07-29 at 11:53 +0200, Enric Balletbo Serra wrote:
> Hi Weiyu,
>
> Thanks for the patch, some comments below. I am not sure what
> maintainers think but your patches, in general, are really big and I'm
> wondering if wouldn't be better split by functionalities. Will make
> your series much longer but easy to review in my opinion. Anyway, I'm
> going to comment a few files but the comments can be applied to other
> files.
>
Hi Enric,
You're right, these are big. I was trying to to add these documents
through the clock series at this stage. Do you suggest to send with
other functional series instead through the clock series?
> Missatge de Weiyi Lu <weiyi.lu@mediatek.com> del dia dc., 29 de jul.
> 2020 a les 10:46:
> >
> > This patch adds the binding documentation for apmixedsys, audsys,
> > camsys-raw, camsys, imgsys, imp_iic_wrap, infracfg, ipesys, mdpsys,
> > mfgcfg, mmsys, msdc, pericfg, scp-adsp, topckgen, vdecsys-soc,
> > vdecsys and vencsys for Mediatek MT8192.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> > .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,camsys-raw.yaml | 40 ++++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,camsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,imgsys.txt | 2 +
> > .../arm/mediatek/mediatek,imp_iic_wrap.yaml | 43 ++++++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,ipesys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,mdpsys.yaml | 38 +++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,msdc.yaml | 39 ++++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 +
> > .../bindings/arm/mediatek/mediatek,scp-adsp.yaml | 38 +++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
> > .../arm/mediatek/mediatek,vdecsys-soc.yaml | 38 +++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,vencsys.txt | 1 +
> > 18 files changed, 249 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > index bd7a0fa..6942ad4 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > @@ -17,6 +17,7 @@ Required Properties:
> > - "mediatek,mt8135-apmixedsys"
> > - "mediatek,mt8173-apmixedsys"
> > - "mediatek,mt8183-apmixedsys", "syscon"
> > + - "mediatek,mt8192-apmixedsys", "syscon"
> > - "mediatek,mt8516-apmixedsys"
> > - #clock-cells: Must be 1
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > index 38309db..fdcb267 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > @@ -12,6 +12,7 @@ Required Properties:
> > - "mediatek,mt7622-audsys", "syscon"
> > - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
> > - "mediatek,mt8183-audiosys", "syscon"
> > + - "mediatek,mt8192-audsys", "syscon"
> > - "mediatek,mt8516-audsys", "syscon"
> > - #clock-cells: Must be 1
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> > new file mode 100644
> > index 0000000..db6f425
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
> > @@ -0,0 +1,40 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,camsys-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!3w84XoXGRAkVX5zxTBA4o5h7EkKiKBuCO5VZDMmx94qoJK357wbTnjT9XN6SRPQc$
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3w84XoXGRAkVX5zxTBA4o5h7EkKiKBuCO5VZDMmx94qoJK357wbTnjT9XGLX7Fq7$
> > +
> > +title: MediaTek CAMSYS RAW Controller
> > +
> > +maintainers:
> > + - Weiyi Lu <weiyi.lu@mediatek.com>
> > +
> > +description:
> > + The Mediatek camsys raw controller provides various clocks to the system.
> > +
>
> It only provides clocks or also provides configuration registers
> non-clock related?
>
Thanks for reminding, it also provides other configuration registers.
I'll update the description in next version.
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8192-camsys_rawa
> > + - mediatek,mt8192-camsys_rawb
> > + - mediatek,mt8192-camsys_rawc
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +examples:
> > + - |
> > + camsys_rawa: camsys_rawa@1a04f000 {
>
> I think that this should be "syscon@1a04f000", since node names are
> supposed to match the class of the device instead of the name of the
> device.
>
Got it, I'll fix in next version.
> Just because I am curious, can you show me an example of
> "mediatek,mt8192-camsys_rawb" or "mediatek,mt8192-camsys_rawc"? It's a
> different address space?
>
> > + compatible = "mediatek,mt8192-camsys_rawa", "syscon";
> > + reg = <0 0x1a04f000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
>
OK, I'll add those in next version.
> [snip]
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next prev parent reply other threads:[~2020-08-11 7:03 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 8:44 [PATCH v2 0/5] Mediatek MT8192 clock support Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
2020-07-29 9:53 ` Enric Balletbo Serra
2020-08-11 7:01 ` Weiyi Lu [this message]
2020-07-29 8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-07-29 10:51 ` Nicolas Boichat
2020-07-29 11:02 ` Nicolas Boichat
2020-08-11 6:34 ` Weiyi Lu
2020-08-11 6:50 ` Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-07-29 10:58 ` Nicolas Boichat
2020-08-11 6:43 ` Weiyi Lu
2020-08-11 7:28 ` Nicolas Boichat
2020-08-11 9:31 ` Weiyi Lu
[not found] ` <1596012277-8448-6-git-send-email-weiyi.lu@mediatek.com>
2020-07-29 9:32 ` [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support Enric Balletbo Serra
2020-08-11 7:03 ` Weiyi Lu
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