From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAC90C433E6 for ; Mon, 31 Aug 2020 08:04:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95D35206F0 for ; Mon, 31 Aug 2020 08:04:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L5RAf0CH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 95D35206F0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=MWiFkAnd2rnzw/Vq/aHbAUnHZiGW96XjpYCjmON4bis=; b=L5RAf0CHsTpge96XjLtjgQvOF4 i7nGkzzBUdhEXniC0Y+ITmlIF/pWGM5AWQhZ6HOVLTA/7X6nDbSkFD9b+KN3zGMALekfctRfQ75w8 NCtjev701bxGd7pAMa6CH57t/Qf5jJImKDHgUIqTsJLa1wUmuE5nfMQ9+TmPD+9t3phTIwTXwIrHr arISihstkgFo3jNa04hIPWtzJIsCpidZDsMZINYZEW7BgxTXQiLC7mKseZIZXX3WS0kPiXFMkAP8m cVoAp/zSgxg2qw/icWDyozOeBpkIsEwFQp2PA5PtoFz1zG0sJecVvUpCBeOf6ncsOYjm6WSionS6t q6ZNRK9Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kCemT-0005zw-30; Mon, 31 Aug 2020 08:03:09 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kCemQ-0005yt-H7 for linux-arm-kernel@lists.infradead.org; Mon, 31 Aug 2020 08:03:07 +0000 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 5A3EE64B80E85D58CA2C; Mon, 31 Aug 2020 16:02:57 +0800 (CST) Received: from SZX1000512381.huawei.com (10.21.83.30) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Mon, 31 Aug 2020 16:02:47 +0800 From: Jonathan Zhou To: Subject: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace Date: Mon, 31 Aug 2020 16:02:46 +0800 Message-ID: <1598860966-70616-1-git-send-email-jonathan.zhouwen@huawei.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.21.83.30] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200831_040306_842816_10B665E2 X-CRM114-Status: GOOD ( 13.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , Catalin Marinas , Will Deacon , Jonathan Zhou , Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4 Self-hosted Trace Extensions. It provides control of exception levels and security states. Let's add this feature detection and enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is supported. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Shaokun Zhang Signed-off-by: Jonathan Zhou --- arch/arm64/include/asm/sysreg.h | 8 ++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 554a7e8ecb07..53da5f326667 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -184,6 +184,13 @@ #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +/* Trace Filter control */ +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) +/* Trace is allowed at EL0 */ +#define SYS_TRFCR_EL1_E0TRE BIT(0) +/* Trace is allowed at EL1 */ +#define SYS_TRFCR_EL1_E1TRE BIT(1) + #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) @@ -772,6 +779,7 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 96425e818fc2..f72b457c2bad 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info) CS_LOCK(drvdata->base); } +static void etm4_init_sysctrl(void *info) +{ + u64 sys_trfcr_el1, dfr0; + int trace_filt; + + dfr0 = read_sysreg(id_aa64dfr0_el1); + + trace_filt = cpuid_feature_extract_unsigned_field(dfr0, + ID_AA64DFR0_SELF_HOSTED_SHIFT); + /* if selfhosted trace implemented, enable trace EL0 as default. */ + if (trace_filt == 0x1) { + sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1); + write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE, + SYS_TRFCR_EL1); + isb(); + } +} + static void etm4_set_default_config(struct etmv4_config *config) { /* disable all events tracing */ @@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etm4_init_arch_data, drvdata, 1)) dev_err(dev, "ETM arch init failed\n"); + if (smp_call_function_single(drvdata->cpu, + etm4_init_sysctrl, drvdata, 1)) + dev_err(dev, "ETM sysctrl init failed\n"); + ret = etm4_pm_setup_cpuslocked(); cpus_read_unlock(); -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel