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Tue, 12 Jan 2021 01:15:53 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 12 Jan 2021 01:15:53 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 12 Jan 2021 01:15:53 -0600 Received: from [10.250.235.36] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10C7FmkX028581; Tue, 12 Jan 2021 01:15:49 -0600 Subject: Re: [PATCH v7 0/2] PCI: cadence: Retrain Link to work around Gen2 To: Nadeem Athani , , , , , , , , References: <20201230120515.2348-1-nadeem@cadence.com> From: Kishon Vijay Abraham I Message-ID: <15abdca0-d1e1-64b7-4a9a-d7549f035e01@ti.com> Date: Tue, 12 Jan 2021 12:45:47 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201230120515.2348-1-nadeem@cadence.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210112_021608_370332_FEE18D39 X-CRM114-Status: GOOD ( 18.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mparab@cadence.com, pthombar@cadence.com, sjakhade@cadence.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 30/12/20 5:35 pm, Nadeem Athani wrote: > Cadence controller will not initiate autonomous speed change if strapped > as Gen2. The Retrain Link bit is set as quirk to enable this speed change. > Adding a quirk flag for defective IP. In future IP revisions this will not > be applicable. > > Version history: > Changes in v7: > - Changing the commit title of patch 1 in this series. > - Added a return value for function cdns_pcie_retrain(). > Changes in v6: > - Move the position of function cdns_pcie_host_wait_for_link to remove > compilation error. No changes in code. Separate patch for this. > Changes in v5: > - Remove the compatible string based setting of quirk flag. > - Removed additional Link Up Check > - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c > Changes in v4: > - Added a quirk flag based on a new compatible string. > - Change of api for link up: cdns_pcie_host_wait_for_link(). > Changes in v3: > - To set retrain link bit,checking device capability & link status. > - 32bit read in place of 8bit. > - Minor correction in patch comment. > - Change in variable & macro name. > Changes in v2: > - 16bit read in place of 8bit. Could get GEN2 card enumerated in GEN2 mode in J7ES EVM. Tested-by: Kishon Vijay Abraham I Thanks Kishon > > Nadeem Athani (2): > PCI: cadence: Shifting of a function to support new code. > PCI: cadence: Retrain Link to work around Gen2 training defect. > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > drivers/pci/controller/cadence/pcie-cadence-host.c | 70 ++++++++++++++++------ > drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- > 3 files changed, 65 insertions(+), 19 deletions(-) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel