From: Stephen Boyd <swboyd@chromium.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: "Isaac J. Manjarres" <isaacm@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs
Date: Tue, 15 Sep 2020 09:01:31 -0700 [thread overview]
Message-ID: <160018569116.4188128.2203705723693537391@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <590f9bacf06d735a7961ddb8234299ca@codeaurora.org>
Quoting Sai Prakash Ranjan (2020-09-14 22:22:45)
>
> As a side note, I have your mails in my inbox but these
> messages are not appearing in the list [1]. For Patch 2,
> its on the list [2]. I have noticed same thing on your
> messages for previous patches, where your reply for one
> patch was on the list but the other one was missing, you
> might have to check that.
I think my MUA has a hard time sometimes. I don't know how to fix it
besides switching away from it to something else. Seems that it can't
handle UTF-8 encoding properly and sends the wrong content-type headers.
>
> [1] https://lore.kernel.org/patchwork/patch/1305132/
> [2] https://lore.kernel.org/patchwork/patch/1305133/
>
> Same with lore.kernel.org/lkml/ links but since url was big, I gave the
> above patchwork links.
>
The lore stuff seems slow sometimes. I see it on lore now:
https://lore.kernel.org/r/160010909573.4188128.171199552773965552@swboyd.mtv.corp.google.com
https://lore.kernel.org/r/160010921920.4188128.15524650302574745988@swboyd.mtv.corp.google.com
maybe I'm hitting spam filters and have to be allowed through. Don't
know.
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prev parent reply other threads:[~2020-09-15 16:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-14 11:12 [PATCHv4 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs Sai Prakash Ranjan
2020-09-14 11:12 ` [PATCHv4 1/2] soc: qcom: llcc: Move attribute config to its own function Sai Prakash Ranjan
2020-09-14 18:44 ` Stephen Boyd
2020-09-15 5:25 ` Sai Prakash Ranjan
2020-09-14 11:13 ` [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs Sai Prakash Ranjan
2020-09-14 18:46 ` Stephen Boyd
2020-09-15 5:22 ` Sai Prakash Ranjan
2020-09-15 16:01 ` Stephen Boyd [this message]
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