[PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[John Garry]

Currently event aliasing and metrics for only CPU and uncore PMUs is
supported. In fact, only uncore PMUs aliasing is supported for when the
uncore PMUs are fixed for a CPU, which may not always be the case for
certain architectures.

This series adds support for PMU event aliasing and metrics for system and
other uncore PMUs which are not tied to a specific CPU.

For this, we introduce system event tables in generated pmu-events.c,
which contain a per-SoC table of events of all its system PMUs. Each
per-PMU event is matched by a "COMPAT" property.

When creating aliased and metrics PMUs, we treat core/uncore and
system PMUs differently:

- For CPU PMUs, we always match for the event mapfile based on the CPUID.
  This has not changed.

- For an system PMUs, we iterate through all the events in all the system
  PMU tables.

  Matches are based on the "COMPAT" property matching the PMU sysfs
  identifier contents, in /sys/bus/event_source/devices/<PMU>/identifier

  Uncore PMUs, may be matched via CPUID or same as system PMU, depending
  on whether the uncore PMU is tied to a specific CPUID.

Initial reference support is also added for ARM SMMUv3 PMCG (Performance
Monitor Event Group) PMU for HiSilicon hip09 platform with only a single
event so far - see driver in drivers/perf/arm_smmuv3_pmu.c reference.

Here is a sample output with this series on Huawei D06CS board:

root@ubuntu:/# ./perf list
   [...]

smmu v3 pmcg:
   smmuv3_pmcg.config_cache_miss
        [Configuration cache miss caused by transaction or(ATS or
        non-ATS)translation request. Unit: smmuv3_pmcg]
   smmuv3_pmcg.config_struct_access
        [Configuration structure access. Unit: smmuv3_pmcg]
   smmuv3_pmcg.cycles
        [Clock cycles. Unit: smmuv3_pmcg]
   smmuv3_pmcg.l1_tlb
        [SMMUv3 PMCG L1 TABLE transation. Unit: smmuv3_pmcg]
   smmuv3_pmcg.pcie_ats_trans_passed
        [PCIe ATS Translated Transaction passed through SMMU. Unit: 
smmuv3_pmcg]
   smmuv3_pmcg.pcie_ats_trans_rq
        [PCIe ATS Translation Request received. Unit: smmuv3_pmcg]
   smmuv3_pmcg.tlb_miss
        [TLB miss caused by incomingtransaction or (ATS or non-ATS) 
translation request. Unit: smmuv3_pmcg]
   smmuv3_pmcg.trans_table_walk_access
        [Translation table walk access. Unit: smmuv3_pmcg]
   smmuv3_pmcg.transaction
        [Transaction. Unit: smmuv3_pmcg]


root@ubuntu:/# ./perf stat -v -e smmuv3_pmcg.l1_tlb sleep 1
Using CPUID 0x00000000480fd010
Using SYSID HIP08
-> smmuv3_pmcg_200100020/event=0x8a/
-> smmuv3_pmcg_200140020/event=0x8a/
-> smmuv3_pmcg_100020/event=0x8a/
-> smmuv3_pmcg_140020/event=0x8a/
-> smmuv3_pmcg_200148020/event=0x8a/
-> smmuv3_pmcg_148020/event=0x8a/
smmuv3_pmcg.l1_tlb: 0 1001221690 1001221690
smmuv3_pmcg.l1_tlb: 0 1001220090 1001220090
smmuv3_pmcg.l1_tlb: 101 1001219660 1001219660
smmuv3_pmcg.l1_tlb: 0 1001219010 1001219010
smmuv3_pmcg.l1_tlb: 0 1001218360 1001218360
smmuv3_pmcg.l1_tlb: 134 1001217850 1001217850

Performance counter stats for 'system wide':

                235      smmuv3_pmcg.l1_tlb 

        1.001263128 seconds time elapsed

root@ubuntu:/#

Support is also added for imx8mm DDR PMU and HiSilicon hip09 uncore events.
Some events for hip09 may not be accurate at the moment.

Series is here:
https://github.com/hisilicon/kernel-dev/tree/private-topic-perf-5.9-sys-pmu-events-v4

Kernel part is here:
https://lore.kernel.org/lkml/1602149181-237415-1-git-send-email-john.garry@huawei.com/T/#mc34f758ab72f3d4a90d854b9bda7e6bbb90835b2

Differences to v3:
- Rebase to v5.9-rc7
- Includes Ian's uncore metric expressions Fix and another fix
- Add hip09 uncore events
- Tidy jevents.c changes a bit

Differences to v2:
- fixups for imx8mm JSONs
- fix for metrics being repeated per PMU
- use sysfs__read_str()
- fix typo in PMCG JSON
- drop evsel fix, which someone else fixed

Differences to v1:
- Stop using SoC id and use a per-PMU identifier instead
- Add metric group sys events support
   - This is a bit hacky
- Add imx8mm DDR Perf support
- Add fix for parse events sel
	- without it, I get this spewed for metric event:

	assertion failed at util/parse-events.c:1637

Ian Rogers (1):
  perf metricgroup: Fix uncore metric expressions

Joakim Zhang (1):
  perf vendor events: Add JSON metrics for imx8mm DDR Perf

John Garry (11):
  perf jevents: Add support for an extra directory level
  perf jevents: Add support for system events tables
  perf pmu: Add pmu_id()
  perf pmu: Add pmu_add_sys_aliases()
  perf vendor events arm64: Add Architected events smmuv3-pmcg.json
  perf vendor events arm64: Add hip09 SMMUv3 PMCG events
  perf vendor events arm64: Add hip09 uncore events
  perf metricgroup: Hack a fix for aliases when covering multiple PMUs
  perf metricgroup: Split up metricgroup__print()
  perf metricgroup: Support printing metric groups for system PMUs
  perf metricgroup: Support adding metrics for system PMUs

 .../arch/arm64/freescale/imx8mm/sys/ddrc.json |  39 +++
 .../arm64/freescale/imx8mm/sys/metrics.json   |  18 +
 .../hisilicon/hip09/sys/smmu-v3-pmcg.json     |  42 +++
 .../hisilicon/hip09/sys/uncore-ddrc.json      |  58 ++++
 .../arm64/hisilicon/hip09/sys/uncore-hha.json |  82 +++++
 .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 106 ++++++
 .../pmu-events/arch/arm64/smmuv3-pmcg.json    |  58 ++++
 tools/perf/pmu-events/jevents.c               | 136 ++++++--
 tools/perf/pmu-events/jevents.h               |  11 +-
 tools/perf/pmu-events/pmu-events.h            |   6 +
 tools/perf/util/metricgroup.c                 | 322 +++++++++++++-----
 tools/perf/util/pmu.c                         |  96 ++++++
 tools/perf/util/pmu.h                         |   3 +
 13 files changed, 863 insertions(+), 114 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json

-- 
2.26.2


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[PATCH RFC v4 01/13] perf jevents: Add support for an extra directory level

[John Garry]

Currently only upto a level 2 directory is supported, in form
vendor/platform.

Add support for a further level, to support vendor/platform
sub-directories in future.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/pmu-events/jevents.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index fc9c158bfa13..6ab96c8dbc27 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -981,15 +981,20 @@ static int process_one_file(const char *fpath, const struct stat *sb,
 	int level   = ftwbuf->level;
 	int err = 0;
 
-	if (level == 2 && is_dir) {
+	if (level >= 2 && is_dir) {
+		int count = 0;
 		/*
 		 * For level 2 directory, bname will include parent name,
 		 * like vendor/platform. So search back from platform dir
 		 * to find this.
+		 * Something similar for level 3 directory, but we're a PMU
+		 * category folder, like vendor/platform/cpu.
 		 */
 		bname = (char *) fpath + ftwbuf->base - 2;
 		for (;;) {
 			if (*bname == '/')
+				count++;
+			if (count == level - 1)
 				break;
 			bname--;
 		}
@@ -1002,13 +1007,13 @@ static int process_one_file(const char *fpath, const struct stat *sb,
 		 level, sb->st_size, bname, fpath);
 
 	/* base dir or too deep */
-	if (level == 0 || level > 3)
+	if (level == 0 || level > 4)
 		return 0;
 
 
 	/* model directory, reset topic */
 	if ((level == 1 && is_dir && is_leaf_dir(fpath)) ||
-	    (level == 2 && is_dir)) {
+	    (level >= 2 && is_dir && is_leaf_dir(fpath))) {
 		if (close_table)
 			print_events_table_suffix(eventsfp);
 
-- 
2.26.2


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[PATCH RFC v4 02/13] perf jevents: Add support for system events tables

[John Garry]

Process the JSONs to find support for "system" events, which are not tied
to a specific CPUID.

A "COMPAT" property is now used to match against the namespace ID from the
kernel PMU driver.

The generated pmu-events.c will now have 2 tables:
a. CPU events, as before.
b. New pmu_sys_event_tables[] table, which will have events matched to
   specific SoCs.

It will look like this:

struct pmu_event pme_hisilicon_hip08_sys[] = {
{
	.name = "cycles",
	.compat = "0x00030736",
	.event = "event=0",
	.desc = "Clock cycles",
	.topic = "smmu v3 pmcg",
	.long_desc = "Clock cycles",
},
{
	.name = "smmuv3_pmcg.l1_tlb",
	.compat = "0x00030736",
	.event = "event=0x8a",
	.desc = "SMMUv3 PMCG l1_tlb. Unit: smmuv3_pmcg ",
	.topic = "smmu v3 pmcg",
	.long_desc = "SMMUv3 PMCG l1_tlb",
	.pmu = "smmuv3_pmcg",
},
...
};

struct pmu_event pme_arm_cortex_a53[] = {
{
	.name = "ext_mem_req",
	.event = "event=0xc0",
	.desc = "External memory request",
	.topic = "memory",
},
{
	.name = "ext_mem_req_nc",
	.event = "event=0xc1",
	.desc = "Non-cacheable external memory request",
	.topic = "memory",
},
...
};

struct pmu_event pme_hisilicon_hip08_cpu[] = {
{
	.name = "l2d_cache_refill_wr",
	.event = "event=0x53",
	.desc = "L2D cache refill, write",
	.topic = "core imp def",
	.long_desc = "Attributable Level 2 data cache refill, write",
},
...
};

struct pmu_events_map pmu_events_map[] = {
{
	.cpuid = "0x00000000410fd030",
	.version = "v1",
	.type = "core",
	.table = pme_arm_cortex_a53
},
{
	.cpuid = "0x00000000480fd010",
	.version = "v1",
	.type = "core",
	.table = pme_hisilicon_hip08_cpu
},
	{
		.table = 0
	},
};

struct pmu_event pme_hisilicon_hip08_cpu[] = {
{
	.name = "uncore_hisi_l3c.rd_cpipe",
	.event = "event=0",
	.desc = "Total read accesses. Unit: hisi_sccl,l3c ",
	.topic = "uncore l3c",
	.long_desc = "Total read accesses",
	.pmu = "hisi_sccl,l3c",
},
{
	.name = "uncore_hisi_l3c.wr_cpipe",
	.event = "event=0x1",
	.desc = "Total write accesses. Unit: hisi_sccl,l3c ",
	.topic = "uncore l3c",
	.long_desc = "Total write accesses",
	.pmu = "hisi_sccl,l3c",
},
...
};


struct pmu_sys_events pmu_sys_event_tables[] = {
{
	.table = pme_hisilicon_hip08_sys,
},
...
};

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/pmu-events/jevents.c    | 122 +++++++++++++++++++++++------
 tools/perf/pmu-events/jevents.h    |  11 ++-
 tools/perf/pmu-events/pmu-events.h |   6 ++
 3 files changed, 108 insertions(+), 31 deletions(-)

diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 6ab96c8dbc27..a1a4bc543a80 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -53,6 +53,23 @@
 int verbose;
 char *prog;
 
+static LIST_HEAD(sys_event_tables);
+
+struct sys_event_table {
+	struct list_head list;
+	char *soc_id;
+};
+
+static void free_sys_event_tables(void)
+{
+	struct sys_event_table *et, *next;
+
+	list_for_each_entry_safe(et, next, &sys_event_tables, list) {
+		free(et->soc_id);
+		free(et);
+	}
+}
+
 int eprintf(int level, int var, const char *fmt, ...)
 {
 
@@ -318,12 +335,12 @@ static void print_events_table_prefix(FILE *fp, const char *tblname)
 	close_table = 1;
 }
 
-static int print_events_table_entry(void *data, char *name, char *event,
-				    char *desc, char *long_desc,
+static int print_events_table_entry(void *data, char *name, char *compat,
+				    char *event, char *desc, char *long_desc,
 				    char *pmu, char *unit, char *perpkg,
-				    char *metric_expr,
-				    char *metric_name, char *metric_group,
-				    char *deprecated, char *metric_constraint)
+				    char *metric_expr, char *metric_name,
+				    char *metric_group, char *deprecated,
+				    char *metric_constraint)
 {
 	struct perf_entry_data *pd = data;
 	FILE *outfp = pd->outfp;
@@ -337,6 +354,9 @@ static int print_events_table_entry(void *data, char *name, char *event,
 
 	if (name)
 		fprintf(outfp, "\t.name = \"%s\",\n", name);
+	if (compat)
+		fprintf(outfp, "\t.compat = \"%s\",\n", compat);
+
 	if (event)
 		fprintf(outfp, "\t.event = \"%s\",\n", event);
 	fprintf(outfp, "\t.desc = \"%s\",\n", desc);
@@ -367,6 +387,7 @@ static int print_events_table_entry(void *data, char *name, char *event,
 struct event_struct {
 	struct list_head list;
 	char *name;
+	char *compat;
 	char *event;
 	char *desc;
 	char *long_desc;
@@ -421,11 +442,12 @@ static void free_arch_std_events(void)
 	}
 }
 
-static int save_arch_std_events(void *data, char *name, char *event,
-				char *desc, char *long_desc, char *pmu,
-				char *unit, char *perpkg, char *metric_expr,
-				char *metric_name, char *metric_group,
-				char *deprecated, char *metric_constraint)
+static int save_arch_std_events(void *data, char *name, char *compat,
+				char *event, char *desc, char *long_desc,
+				char *pmu, char *unit, char *perpkg,
+				char *metric_expr, char *metric_name,
+				char *metric_group, char *deprecated,
+				char *metric_constraint)
 {
 	struct event_struct *es;
 
@@ -513,12 +535,11 @@ try_fixup(const char *fn, char *arch_std, char **event, char **desc,
 
 /* Call func with each event in the json file */
 int json_events(const char *fn,
-	  int (*func)(void *data, char *name, char *event, char *desc,
-		      char *long_desc,
-		      char *pmu, char *unit, char *perpkg,
-		      char *metric_expr,
-		      char *metric_name, char *metric_group,
-		      char *deprecated, char *metric_constraint),
+	  int (*func)(void *data, char *name, char *compat, char *event,
+		      char *desc, char *long_desc, char *pmu, char *unit,
+		      char *perpkg, char *metric_expr, char *metric_name,
+		      char *metric_group, char *deprecated,
+		      char *metric_constraint),
 	  void *data)
 {
 	int err;
@@ -537,7 +558,7 @@ int json_events(const char *fn,
 	EXPECT(tokens->type == JSMN_ARRAY, tokens, "expected top level array");
 	tok = tokens + 1;
 	for (i = 0; i < tokens->size; i++) {
-		char *event = NULL, *desc = NULL, *name = NULL;
+		char *event = NULL, *desc = NULL, *name = NULL, *compat = NULL;
 		char *long_desc = NULL;
 		char *extra_desc = NULL;
 		char *pmu = NULL;
@@ -584,6 +605,8 @@ int json_events(const char *fn,
 				free(code);
 			} else if (json_streq(map, field, "EventName")) {
 				addfield(map, &name, "", "", val);
+			} else if (json_streq(map, field, "Compat")) {
+				addfield(map, &compat, "", "", val);
 			} else if (json_streq(map, field, "BriefDescription")) {
 				addfield(map, &desc, "", "", val);
 				fixdesc(desc);
@@ -680,13 +703,15 @@ int json_events(const char *fn,
 			if (err)
 				goto free_strings;
 		}
-		err = func(data, name, real_event(name, event), desc, long_desc,
-			   pmu, unit, perpkg, metric_expr, metric_name,
-			   metric_group, deprecated, metric_constraint);
+		err = func(data, name, compat, real_event(name, event), desc,
+			   long_desc, pmu, unit, perpkg, metric_expr,
+			   metric_name, metric_group, deprecated,
+			   metric_constraint);
 free_strings:
+		free(name);
+		free(compat);
 		free(event);
 		free(desc);
-		free(name);
 		free(long_desc);
 		free(extra_desc);
 		free(pmu);
@@ -750,6 +775,15 @@ static char *file_name_to_table_name(char *fname)
 	return tblname;
 }
 
+static bool is_sys_dir(char *fname)
+{
+	size_t len = strlen(fname), len2 = strlen("/sys");
+
+	if (len2 > len)
+		return false;
+	return !strcmp(fname+len-len2, "/sys");
+}
+
 static void print_mapping_table_prefix(FILE *outfp)
 {
 	fprintf(outfp, "struct pmu_events_map pmu_events_map[] = {\n");
@@ -784,6 +818,23 @@ static void print_mapping_test_table(FILE *outfp)
 	fprintf(outfp, "},\n");
 }
 
+static int process_system_event_tables(FILE *outfp)
+{
+	struct sys_event_table *sys_event_table;
+
+	fprintf(outfp, "\nstruct pmu_sys_events pmu_sys_event_tables[] = {");
+
+	list_for_each_entry(sys_event_table, &sys_event_tables, list) {
+		fprintf(outfp, "\n\t{\n\t\t.table = %s,\n\t},",
+			sys_event_table->soc_id);
+	}
+	fprintf(outfp, "\n\t{\n\t\t.table = 0\n\t},");
+
+	fprintf(outfp, "\n};\n");
+
+	return 0;
+}
+
 static int process_mapfile(FILE *outfp, char *fpath)
 {
 	int n = 16384;
@@ -1029,6 +1080,22 @@ static int process_one_file(const char *fpath, const struct stat *sb,
 			return -1;
 		}
 
+		if (is_sys_dir(bname)) {
+			struct sys_event_table *sys_event_table;
+
+			sys_event_table = malloc(sizeof(*sys_event_table));
+			if (!sys_event_table)
+				return -1;
+
+			sys_event_table->soc_id = strdup(tblname);
+			if (!sys_event_table->soc_id) {
+				free(sys_event_table);
+				return -1;
+			}
+			list_add_tail(&sys_event_table->list,
+				      &sys_event_tables);
+		}
+
 		print_events_table_prefix(eventsfp, tblname);
 		return 0;
 	}
@@ -1180,7 +1247,6 @@ int main(int argc, char *argv[])
 	} else if (rc < 0) {
 		/* Make build fail */
 		fclose(eventsfp);
-		free_arch_std_events();
 		ret = 1;
 		goto out_free_mapfile;
 	} else if (rc) {
@@ -1212,21 +1278,27 @@ int main(int argc, char *argv[])
 	}
 
 	if (process_mapfile(eventsfp, mapfile)) {
-		pr_info("%s: Error processing mapfile %s\n", prog, mapfile);
+		pr_err("%s: Error processing mapfile %s\n", prog,
+		       mapfile);
 		/* Make build fail */
 		fclose(eventsfp);
-		free_arch_std_events();
 		ret = 1;
+		goto out_free_mapfile;
 	}
 
+	if (process_system_event_tables(eventsfp)) {
+		fclose(eventsfp);
+		ret = 1;
+	}
 
 	goto out_free_mapfile;
 
 empty_map:
 	fclose(eventsfp);
 	create_empty_mapping(output_file);
-	free_arch_std_events();
 out_free_mapfile:
+	free_arch_std_events();
+	free_sys_event_tables();
 	free(mapfile);
 	return ret;
 }
diff --git a/tools/perf/pmu-events/jevents.h b/tools/perf/pmu-events/jevents.h
index 2afc8304529e..7e324b210747 100644
--- a/tools/perf/pmu-events/jevents.h
+++ b/tools/perf/pmu-events/jevents.h
@@ -3,12 +3,11 @@
 #define JEVENTS_H 1
 
 int json_events(const char *fn,
-		int (*func)(void *data, char *name, char *event, char *desc,
-				char *long_desc,
-				char *pmu,
-				char *unit, char *perpkg, char *metric_expr,
-				char *metric_name, char *metric_group,
-				char *deprecated, char *metric_constraint),
+		int (*func)(void *data, char *name, char *compat, char *event,
+			    char *desc, char *long_desc, char *pmu, char *unit,
+			    char *perpkg, char *metric_expr, char *metric_name,
+			    char *metric_group, char *deprecated,
+			    char *metric_constraint),
 		void *data);
 char *get_cpu_str(void);
 
diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h
index c8f306b572f4..7b8f802e872b 100644
--- a/tools/perf/pmu-events/pmu-events.h
+++ b/tools/perf/pmu-events/pmu-events.h
@@ -7,6 +7,7 @@
  */
 struct pmu_event {
 	const char *name;
+	const char *compat;
 	const char *event;
 	const char *desc;
 	const char *topic;
@@ -37,10 +38,15 @@ struct pmu_events_map {
 	struct pmu_event *table;
 };
 
+struct pmu_sys_events {
+	struct pmu_event *table;
+};
+
 /*
  * Global table mapping each known CPU for the architecture to its
  * table of PMU events.
  */
 extern struct pmu_events_map pmu_events_map[];
+extern struct pmu_sys_events pmu_sys_event_tables[];
 
 #endif
-- 
2.26.2


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[PATCH RFC v4 03/13] perf pmu: Add pmu_id()

[John Garry]

Add a function to read the PMU id sysfs entry. This is only done for uncore
PMUs where this would possibly be relevant.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/pmu.c | 18 ++++++++++++++++++
 tools/perf/util/pmu.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index d41caeb35cf6..cbeda45ce578 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -597,6 +597,7 @@ static struct perf_cpu_map *__pmu_cpumask(const char *path)
  * Uncore PMUs have a "cpumask" file under sysfs. CPU PMUs (e.g. on arm/arm64)
  * may have a "cpus" file.
  */
+#define SYS_TEMPLATE_ID	"./bus/event_source/devices/%s/identifier"
 #define CPUS_TEMPLATE_UNCORE	"%s/bus/event_source/devices/%s/cpumask"
 #define CPUS_TEMPLATE_CPU	"%s/bus/event_source/devices/%s/cpus"
 
@@ -635,6 +636,21 @@ static bool pmu_is_uncore(const char *name)
 	return file_available(path);
 }
 
+static char *pmu_id(const char *name)
+{
+	char path[PATH_MAX], *str;
+	size_t len;
+
+	snprintf(path, PATH_MAX, SYS_TEMPLATE_ID, name);
+
+	if (sysfs__read_str(path, &str, &len) < 0)
+		return NULL;
+
+	str[len - 1] = 0; /* remove line feed */
+
+	return str;
+}
+
 /*
  *  PMU CORE devices have different name other than cpu in sysfs on some
  *  platforms.
@@ -847,6 +863,8 @@ static struct perf_pmu *pmu_lookup(const char *name)
 	pmu->name = strdup(name);
 	pmu->type = type;
 	pmu->is_uncore = pmu_is_uncore(name);
+	if (pmu->is_uncore)
+		pmu->id = pmu_id(name);
 	pmu->max_precise = pmu_max_precise(name);
 	pmu_add_cpu_aliases(&aliases, pmu);
 
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index a64e9c9ce731..d4366e8e79df 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -30,6 +30,7 @@ struct perf_pmu_caps {
 
 struct perf_pmu {
 	char *name;
+	char *id;
 	__u32 type;
 	bool selectable;
 	bool is_uncore;
-- 
2.26.2


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[PATCH RFC v4 04/13] perf pmu: Add pmu_add_sys_aliases()

[John Garry]

Add pmu_add_sys_aliases() to add system PMU events aliases.

For adding system PMU events, iterate through all the events for all SoC
event tables in pmu_sys_event_tables[].

Matches must satisfy both:
- PMU identifier matches event "compat" value
- event "Unit" member must match, same as uncore event aliases matched by
  CPUID

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/pmu.c | 78 +++++++++++++++++++++++++++++++++++++++++++
 tools/perf/util/pmu.h |  2 ++
 2 files changed, 80 insertions(+)

diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index cbeda45ce578..44ef28302fc7 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -812,6 +812,83 @@ static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu)
 	pmu_add_cpu_aliases_map(head, pmu, map);
 }
 
+void pmu_for_each_sys_event(pmu_sys_event_iter_fn fn, void *data)
+{
+	int i = 0;
+
+	while (1) {
+		struct pmu_sys_events *event_table;
+		int j = 0;
+
+		event_table = &pmu_sys_event_tables[i++];
+
+		if (!event_table->table)
+			break;
+
+		while (1) {
+			struct pmu_event *pe = &event_table->table[j++];
+			int ret;
+
+			if (!pe->name && !pe->metric_group && !pe->metric_name)
+				break;
+
+			ret = fn(pe, data);
+			if (ret)
+				break;
+		}
+	}
+}
+
+struct pmu_sys_event_iter_data {
+	struct list_head *head;
+	struct perf_pmu *pmu;
+};
+
+static int pmu_add_sys_aliases_iter_fn(struct pmu_event *pe, void *data)
+{
+	struct pmu_sys_event_iter_data *idata = data;
+	struct perf_pmu *pmu = idata->pmu;
+
+	if (!pe->name) {
+		if (pe->metric_group || pe->metric_name)
+			return 0;
+		return -EINVAL;
+	}
+
+	if (!pe->compat || !pe->pmu)
+		return 0;
+
+	if (!strcmp(pmu->id, pe->compat) &&
+	    pmu_uncore_alias_match(pe->pmu, pmu->name)) {
+		__perf_pmu__new_alias(idata->head, NULL,
+				      (char *)pe->name,
+				      (char *)pe->desc,
+				      (char *)pe->event,
+				      (char *)pe->long_desc,
+				      (char *)pe->topic,
+				      (char *)pe->unit,
+				      (char *)pe->perpkg,
+				      (char *)pe->metric_expr,
+				      (char *)pe->metric_name,
+				      (char *)pe->deprecated);
+	}
+
+	return 0;
+}
+
+static void pmu_add_sys_aliases(struct list_head *head, struct perf_pmu *pmu)
+{
+	struct pmu_sys_event_iter_data idata = {
+		.head = head,
+		.pmu = pmu,
+	};
+
+	if (!pmu->id)
+		return;
+
+	pmu_for_each_sys_event(pmu_add_sys_aliases_iter_fn, &idata);
+}
+
 struct perf_event_attr * __weak
 perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
 {
@@ -867,6 +944,7 @@ static struct perf_pmu *pmu_lookup(const char *name)
 		pmu->id = pmu_id(name);
 	pmu->max_precise = pmu_max_precise(name);
 	pmu_add_cpu_aliases(&aliases, pmu);
+	pmu_add_sys_aliases(&aliases, pmu);
 
 	INIT_LIST_HEAD(&pmu->format);
 	INIT_LIST_HEAD(&pmu->aliases);
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index d4366e8e79df..8164388478c6 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -117,6 +117,8 @@ struct pmu_events_map *perf_pmu__find_map(struct perf_pmu *pmu);
 bool pmu_uncore_alias_match(const char *pmu_name, const char *name);
 void perf_pmu_free_alias(struct perf_pmu_alias *alias);
 
+typedef int (*pmu_sys_event_iter_fn)(struct pmu_event *pe, void *data);
+void pmu_for_each_sys_event(pmu_sys_event_iter_fn fn, void *data);
 int perf_pmu__convert_scale(const char *scale, char **end, double *sval);
 
 int perf_pmu__caps_parse(struct perf_pmu *pmu);
-- 
2.26.2


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[PATCH RFC v4 05/13] perf vendor events arm64: Add Architected events smmuv3-pmcg.json

[John Garry]

Add JSON for Architected events from [0], Section 10.3 .

[0] https://static.docs.arm.com/ihi0070/a/IHI_0070A_SMMUv3.pdf

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../pmu-events/arch/arm64/smmuv3-pmcg.json    | 58 +++++++++++++++++++
 tools/perf/pmu-events/jevents.c               |  2 +
 2 files changed, 60 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json

diff --git a/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json
new file mode 100644
index 000000000000..8a59ce48bf06
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json
@@ -0,0 +1,58 @@
+[
+    {
+        "PublicDescription": "Clock cycles",
+        "EventCode": "0x00",
+        "EventName": "smmuv3_pmcg.CYCLES",
+        "BriefDescription": "Clock cycles"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "Transaction",
+        "EventCode": "0x01",
+        "EventName": "smmuv3_pmcg.TRANSACTION",
+        "BriefDescription": "Transaction"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request",
+        "EventCode": "0x02",
+        "EventName": "smmuv3_pmcg.TLB_MISS",
+        "BriefDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request",
+        "EventCode": "0x03",
+        "EventName": "smmuv3_pmcg.CONFIG_CACHE_MISS",
+        "BriefDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "Translation table walk access",
+        "EventCode": "0x04",
+        "EventName": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS",
+        "BriefDescription": "Translation table walk access"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "Configuration structure access",
+        "EventCode": "0x05",
+        "EventName": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS",
+        "BriefDescription": "Configuration structure access"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "PCIe ATS Translation Request received",
+        "EventCode": "0x06",
+        "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ",
+        "BriefDescription": "PCIe ATS Translation Request received"
+        "Unit": "smmuv3_pmcg",
+    },
+    {
+        "PublicDescription": "PCIe ATS Translated Transaction passed through SMMU",
+        "EventCode": "0x07",
+        "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED",
+        "BriefDescription": "PCIe ATS Translated Transaction passed through SMMU"
+        "Unit": "smmuv3_pmcg",
+    }
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index a1a4bc543a80..2e581bd9b0a6 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -256,6 +256,8 @@ static struct map {
 	{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
 	{ "hisi_sccl,hha", "hisi_sccl,hha" },
 	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
+	/* it's not realistic to keep adding these, we need something more scalable ... */
+	{ "smmuv3_pmcg", "smmuv3_pmcg" },
 	{ "L3PMC", "amd_l3" },
 	{}
 };
-- 
2.26.2


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[PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

[John Garry]

Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.

This contains a mix of architected and IMP def events

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../hisilicon/hip09/sys/smmu-v3-pmcg.json     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
new file mode 100644
index 000000000000..8abafbb2dcb4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
@@ -0,0 +1,42 @@
+[
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CYCLES"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "EventCode": "0x8a",
+	    "EventName": "smmuv3_pmcg.L1_TLB",
+	    "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
+	    "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",
+	    "Unit": "smmuv3_pmcg",
+	    "Compat": "0x00030736"
+   },
+]
-- 
2.26.2


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[PATCH RFC v4 07/13] perf vendor events arm64: Add hip09 uncore events

[John Garry]

Add uncore events for DDRC, HHA, and L3C. We use "Compat" property to
match to specific implementations of the PMUs.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../hisilicon/hip09/sys/uncore-ddrc.json      |  58 ++++++++++
 .../arm64/hisilicon/hip09/sys/uncore-hha.json |  82 ++++++++++++++
 .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 106 ++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
new file mode 100644
index 000000000000..a91c97813ae0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
@@ -0,0 +1,58 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_ddrc.cycles",
+	    "BriefDescription": "DDRC total clock cycles",
+	    "PublicDescription": "DDRC total clock cycles",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_ddrc.act_cmd",
+	    "BriefDescription": "DDRC active commands",
+	    "PublicDescription": "DDRC active commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_ddrc.rw_cmd",
+	    "BriefDescription": "DDRC read and write commands",
+	    "PublicDescription": "DDRC read and write commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   }
+   {
+	    "EventCode": "0x04",
+	    "EventName": "uncore_hisi_ddrc.refresh_cmd",
+	    "BriefDescription": "DDRC total refresh commands",
+	    "PublicDescription": "DDRC total refresh commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x05",
+	    "EventName": "uncore_hisi_ddrc.preall_cmd",
+	    "BriefDescription": "DDRC precharge-all commands",
+	    "PublicDescription": "DDRC precharge-all commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x41",
+	    "EventName": "uncore_hisi_ddrc.read_cmd",
+	    "BriefDescription": "DDRC read commands",
+	    "PublicDescription": "DDRC read commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x44",
+	    "EventName": "uncore_hisi_ddrc.write_cmd",
+	    "BriefDescription": "DDRC write commands",
+	    "PublicDescription": "DDRC write commands",
+	    "Unit": "hisi_sccl,ddrc"
+	    "Compat": "0x00000030"
+   }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
new file mode 100644
index 000000000000..5a39f1083ee6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
@@ -0,0 +1,82 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_hha.rx_ops_num",
+	    "BriefDescription": "The number of all operations received by the HHA",
+	    "PublicDescription": "The number of all operations received by the HHA",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_hha.rx_outer",
+	    "BriefDescription": "The number of all operations received by the HHA from another socket",
+	    "PublicDescription": "The number of all operations received by the HHA from another socket",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x02",
+	    "EventName": "uncore_hisi_hha.rx_sccl",
+	    "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",
+	    "PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_hha.rx_ccix",
+	    "BriefDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "PublicDescription": "Count of the number of operations that HHA has received from CCIX",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x1c",
+	    "EventName": "uncore_hisi_hha.rd_ddr_64b",
+	    "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
+	    "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x1d",
+	    "EventName": "uncore_hisi_hha.wr_ddr_64b",
+	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
+	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x1e",
+	    "EventName": "uncore_hisi_hha.rd_ddr_128b",
+	    "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
+	    "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x1f",
+	    "EventName": "uncore_hisi_hha.wr_ddr_128b",
+	    "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
+	    "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_hha.spill_num",
+	    "BriefDescription": "Count of the number of spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_hha.spill_success",
+	    "BriefDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "PublicDescription": "Count of the number of successful spill operations that the HHA has sent",
+	    "Unit": "hisi_sccl,hha"
+	    "Compat": "0x00000030"
+   }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json
new file mode 100644
index 000000000000..3ae7948982ca
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json
@@ -0,0 +1,106 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_l3c.rd_cpipe",
+	    "BriefDescription": "Total read accesses",
+	    "PublicDescription": "Total read accesses",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_l3c.wr_cpipe",
+	    "BriefDescription": "Total write accesses",
+	    "PublicDescription": "Total write accesses",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x02",
+	    "EventName": "uncore_hisi_l3c.rd_hit_cpipe",
+	    "BriefDescription": "Total read hits",
+	    "PublicDescription": "Total read hits",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_l3c.wr_hit_cpipe",
+	    "BriefDescription": "Total write hits",
+	    "PublicDescription": "Total write hits",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x04",
+	    "EventName": "uncore_hisi_l3c.victim_num",
+	    "BriefDescription": "l3c precharge commands",
+	    "PublicDescription": "l3c precharge commands",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x20",
+	    "EventName": "uncore_hisi_l3c.rd_spipe",
+	    "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x21",
+	    "EventName": "uncore_hisi_l3c.wr_spipe",
+	    "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x22",
+	    "EventName": "uncore_hisi_l3c.rd_hit_spipe",
+	    "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x23",
+	    "EventName": "uncore_hisi_l3c.wr_hit_spipe",
+	    "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x29",
+	    "EventName": "uncore_hisi_l3c.back_invalid",
+	    "BriefDescription": "Count of the number of L3C back invalid operations",
+	    "PublicDescription": "Count of the number of L3C back invalid operations",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x40",
+	    "EventName": "uncore_hisi_l3c.retry_cpu",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x41",
+	    "EventName": "uncore_hisi_l3c.retry_ring",
+	    "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   },
+   {
+	    "EventCode": "0x42",
+	    "EventName": "uncore_hisi_l3c.prefetch_drop",
+	    "BriefDescription": "Count of the number of prefetch drops from this L3C",
+	    "PublicDescription": "Count of the number of prefetch drops from this L3C",
+	    "Unit": "hisi_sccl,l3c"
+	    "Compat": "0x00000030"
+   }
+]
-- 
2.26.2


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[PATCH RFC v4 08/13] perf metricgroup: Fix uncore metric expressions

[John Garry]

From: Ian Rogers <irogers@google.com>

A metric like DRAM_BW_Use has on SkylakeX events uncore_imc/cas_count_read/
and uncore_imc/case_count_write/. These events open 6 events per socket
with pmu names of uncore_imc_[0-5]. The current metric setup code in
find_evsel_group assumes one ID will map to 1 event to be recorded in
metric_events. For events with multiple matches, the first event is
recorded in metric_events (avoiding matching >1 event with the same
name) and the evlist_used updated so that duplicate events aren't
removed when the evlist has unused events removed.

Before this change:
$ /tmp/perf/perf stat -M DRAM_BW_Use -a -- sleep 1

 Performance counter stats for 'system wide':

             41.14 MiB  uncore_imc/cas_count_read/
     1,002,614,251 ns   duration_time

       1.002614251 seconds time elapsed

After this change:
$ /tmp/perf/perf stat -M DRAM_BW_Use -a -- sleep 1

 Performance counter stats for 'system wide':

            157.47 MiB  uncore_imc/cas_count_read/ #     0.00 DRAM_BW_Use
            126.97 MiB  uncore_imc/cas_count_write/
     1,003,019,728 ns   duration_time

Erroneous duplication introduced in:
commit 2440689d62e9 ("perf metricgroup: Remove duped metric group events").

Fixes: ded80bda8bc9 ("perf expr: Migrate expr ids table to a hashmap").
Reported-by: Jin Yao <yao.jin@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
---
 tools/perf/util/metricgroup.c | 75 ++++++++++++++++++++++++++---------
 1 file changed, 56 insertions(+), 19 deletions(-)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index ab5030fcfed4..d948a7f910cf 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -150,6 +150,18 @@ static void expr_ids__exit(struct expr_ids *ids)
 		free(ids->id[i].id);
 }
 
+static bool contains_event(struct evsel **metric_events, int num_events,
+			const char *event_name)
+{
+	int i;
+
+	for (i = 0; i < num_events; i++) {
+		if (!strcmp(metric_events[i]->name, event_name))
+			return true;
+	}
+	return false;
+}
+
 /**
  * Find a group of events in perf_evlist that correpond to those from a parsed
  * metric expression. Note, as find_evsel_group is called in the same order as
@@ -180,7 +192,11 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 	int i = 0, matched_events = 0, events_to_match;
 	const int idnum = (int)hashmap__size(&pctx->ids);
 
-	/* duration_time is grouped separately. */
+	/*
+	 * duration_time is always grouped separately, when events are grouped
+	 * (ie has_constraint is false) then ignore it in the matching loop and
+	 * add it to metric_events at the end.
+	 */
 	if (!has_constraint &&
 	    hashmap__find(&pctx->ids, "duration_time", (void **)&val_ptr))
 		events_to_match = idnum - 1;
@@ -207,23 +223,20 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 				sizeof(struct evsel *) * idnum);
 			current_leader = ev->leader;
 		}
-		if (hashmap__find(&pctx->ids, ev->name, (void **)&val_ptr)) {
-			if (has_constraint) {
-				/*
-				 * Events aren't grouped, ensure the same event
-				 * isn't matched from two groups.
-				 */
-				for (i = 0; i < matched_events; i++) {
-					if (!strcmp(ev->name,
-						    metric_events[i]->name)) {
-						break;
-					}
-				}
-				if (i != matched_events)
-					continue;
-			}
+		/*
+		 * Check for duplicate events with the same name. For example,
+		 * uncore_imc/cas_count_read/ will turn into 6 events per socket
+		 * on skylakex. Only the first such event is placed in
+		 * metric_events. If events aren't grouped then this also
+		 * ensures that the same event in different sibling groups
+		 * aren't both added to metric_events.
+		 */
+		if (contains_event(metric_events, matched_events, ev->name))
+			continue;
+		/* Does this event belong to the parse context? */
+		if (hashmap__find(&pctx->ids, ev->name, (void **)&val_ptr))
 			metric_events[matched_events++] = ev;
-		}
+
 		if (matched_events == events_to_match)
 			break;
 	}
@@ -239,7 +252,7 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 	}
 
 	if (matched_events != idnum) {
-		/* Not whole match */
+		/* Not a whole match */
 		return NULL;
 	}
 
@@ -247,8 +260,32 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 
 	for (i = 0; i < idnum; i++) {
 		ev = metric_events[i];
-		ev->metric_leader = ev;
+		/* Don't free the used events. */
 		set_bit(ev->idx, evlist_used);
+		/*
+		 * The metric leader points to the identically named event in
+		 * metric_events.
+		 */
+		ev->metric_leader = ev;
+		/*
+		 * Mark two events with identical names in the same group (or
+		 * globally) as being in use as uncore events may be duplicated
+		 * for each pmu. Set the metric leader of such events to be the
+		 * event that appears in metric_events.
+		 */
+		evlist__for_each_entry_continue(perf_evlist, ev) {
+			/*
+			 * If events are grouped then the search can terminate
+			 * when then group is left.
+			 */
+			if (!has_constraint &&
+			    ev->leader != metric_events[i]->leader)
+				break;
+			if (!strcmp(metric_events[i]->name, ev->name)) {
+				set_bit(ev->idx, evlist_used);
+				ev->metric_leader = metric_events[i];
+			}
+		}
 	}
 
 	return metric_events[0];
-- 
2.26.2


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[PATCH RFC v4 09/13] perf metricgroup: Hack a fix for aliases when covering multiple PMUs

[John Garry]

Function find_evsel_group() seems broken for aliases covering multiple
PMUs, as dicussed at:

https://lore.kernel.org/lkml/CAP-5=fUy6FOszNRwJF6ZNpqQSSyrnLPV6GbkEcZMqAhUp3X0ZA@mail.gmail.com/

For now, hack a fix which I only know works for me.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/metricgroup.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index d948a7f910cf..82ba3638f48c 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -213,7 +213,7 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 		/* Ignore event if already used and merging is disabled. */
 		if (metric_no_merge && test_bit(ev->idx, evlist_used))
 			continue;
-		if (!has_constraint && ev->leader != current_leader) {
+		if (!has_constraint && (!current_leader || strcmp(current_leader->name, ev->leader->name))) {
 			/*
 			 * Start of a new group, discard the whole match and
 			 * start again.
@@ -279,7 +279,7 @@ static struct evsel *find_evsel_group(struct evlist *perf_evlist,
 			 * when then group is left.
 			 */
 			if (!has_constraint &&
-			    ev->leader != metric_events[i]->leader)
+			    strcmp(ev->leader->name, metric_events[i]->leader->name))
 				break;
 			if (!strcmp(metric_events[i]->name, ev->name)) {
 				set_bit(ev->idx, evlist_used);
-- 
2.26.2


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[PATCH RFC v4 10/13] perf metricgroup: Split up metricgroup__print()

[John Garry]

To aid supporting system event metric groups, break up the function
metricgroup__print() into a part which iterates metrics and a part which
actually "prints" the metric.

No functional change intended.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/metricgroup.c | 124 +++++++++++++++++++---------------
 1 file changed, 70 insertions(+), 54 deletions(-)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index 82ba3638f48c..1102391cafeb 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -491,6 +491,72 @@ static void metricgroup__print_strlist(struct strlist *metrics, bool raw)
 		putchar('\n');
 }
 
+static int metricgroup__print_pmu_event(struct pmu_event *pe,
+                                        bool metricgroups, char *filter,
+                                        bool raw, bool details,
+                                        struct rblist *groups,
+                                        struct strlist *metriclist)
+{
+	const char *g;
+	char *omg, *mg;
+
+	g = pe->metric_group;
+	if (!g && pe->metric_name) {
+		if (pe->name)
+			return 0;
+		g = "No_group";
+	}
+
+	if (!g)
+		return 0;
+
+	mg = strdup(g);
+
+	if (!mg)
+		return -ENOMEM;
+	omg = mg;
+	while ((g = strsep(&mg, ";")) != NULL) {
+		struct mep *me;
+		char *s;
+
+		g = skip_spaces(g);
+		if (*g == 0)
+			g = "No_group";
+		if (filter && !strstr(g, filter))
+			continue;
+		if (raw)
+			s = (char *)pe->metric_name;
+		else {
+			if (asprintf(&s, "%s\n%*s%s]",
+				     pe->metric_name, 8, "[", pe->desc) < 0)
+				return -1;
+			if (details) {
+				if (asprintf(&s, "%s\n%*s%s]",
+					     s, 8, "[", pe->metric_expr) < 0)
+					return -1;
+			}
+		}
+
+		if (!s)
+			continue;
+
+		if (!metricgroups) {
+			strlist__add(metriclist, s);
+		} else {
+			me = mep_lookup(groups, g);
+			if (!me)
+				continue;
+			strlist__add(me->metrics, s);
+		}
+
+		if (!raw)
+			free(s);
+	}
+	free(omg);
+
+	return 0;
+}
+
 void metricgroup__print(bool metrics, bool metricgroups, char *filter,
 			bool raw, bool details)
 {
@@ -515,66 +581,16 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter,
 	groups.node_cmp = mep_cmp;
 	groups.node_delete = mep_delete;
 	for (i = 0; ; i++) {
-		const char *g;
 		pe = &map->table[i];
 
 		if (!pe->name && !pe->metric_group && !pe->metric_name)
 			break;
 		if (!pe->metric_expr)
 			continue;
-		g = pe->metric_group;
-		if (!g && pe->metric_name) {
-			if (pe->name)
-				continue;
-			g = "No_group";
-		}
-		if (g) {
-			char *omg;
-			char *mg = strdup(g);
-
-			if (!mg)
-				return;
-			omg = mg;
-			while ((g = strsep(&mg, ";")) != NULL) {
-				struct mep *me;
-				char *s;
-
-				g = skip_spaces(g);
-				if (*g == 0)
-					g = "No_group";
-				if (filter && !strstr(g, filter))
-					continue;
-				if (raw)
-					s = (char *)pe->metric_name;
-				else {
-					if (asprintf(&s, "%s\n%*s%s]",
-						     pe->metric_name, 8, "[", pe->desc) < 0)
-						return;
-
-					if (details) {
-						if (asprintf(&s, "%s\n%*s%s]",
-							     s, 8, "[", pe->metric_expr) < 0)
-							return;
-					}
-				}
-
-				if (!s)
-					continue;
-
-				if (!metricgroups) {
-					strlist__add(metriclist, s);
-				} else {
-					me = mep_lookup(&groups, g);
-					if (!me)
-						continue;
-					strlist__add(me->metrics, s);
-				}
-
-				if (!raw)
-					free(s);
-			}
-			free(omg);
-		}
+		if (metricgroup__print_pmu_event(pe, metricgroups, filter,
+						 raw, details, &groups,
+						 metriclist) < 0)
+			return;
 	}
 
 	if (metricgroups && !raw)
-- 
2.26.2


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[PATCH RFC v4 11/13] perf metricgroup: Support printing metric groups for system PMUs

[John Garry]

Currently printing metricgroups for core- or uncore-based events matched
by CPUID is supported.

Extend this for system events.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/metricgroup.c | 62 +++++++++++++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 3 deletions(-)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index 1102391cafeb..03f811eb600b 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -557,6 +557,49 @@ static int metricgroup__print_pmu_event(struct pmu_event *pe,
 	return 0;
 }
 
+struct metricgroup_print_sys_idata {
+	struct strlist *metriclist;
+	bool metricgroups;
+	char *filter;
+	bool raw;
+	bool details;
+	struct rblist *groups;
+};
+
+typedef int (*metricgroup_sys_event_iter_fn)(struct pmu_event *pe, void *);
+
+struct metricgroup_iter_data {
+	metricgroup_sys_event_iter_fn fn;
+	void *data;
+};
+
+static int metricgroup__sys_event_iter(struct pmu_event *pe, void *data)
+{
+	struct metricgroup_iter_data *d = data;
+	struct perf_pmu *pmu = NULL;
+
+	if (!pe->metric_expr || !pe->compat)
+		return 0;
+
+	while ((pmu = perf_pmu__scan(pmu))) {
+
+		if (!pmu->id || strcmp(pmu->id, pe->compat))
+			continue;
+
+		return d->fn(pe, d->data);
+	}
+
+	return 0;
+}
+
+static int metricgroup__print_sys_event_iter(struct pmu_event *pe, void *data)
+{
+	struct metricgroup_print_sys_idata *d = data;
+
+	return metricgroup__print_pmu_event(pe, d->metricgroups, d->filter, d->raw,
+				     d->details, d->groups, d->metriclist);
+}
+
 void metricgroup__print(bool metrics, bool metricgroups, char *filter,
 			bool raw, bool details)
 {
@@ -567,9 +610,6 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter,
 	struct rb_node *node, *next;
 	struct strlist *metriclist = NULL;
 
-	if (!map)
-		return;
-
 	if (!metricgroups) {
 		metriclist = strlist__new(NULL, NULL);
 		if (!metriclist)
@@ -593,6 +633,22 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter,
 			return;
 	}
 
+	{
+		struct metricgroup_iter_data data = {
+			.fn = metricgroup__print_sys_event_iter,
+			.data = (void *) &(struct metricgroup_print_sys_idata){
+				.metriclist = metriclist,
+				.metricgroups = metricgroups,
+				.filter = filter,
+				.raw = raw,
+				.details = details,
+				.groups = &groups,
+			},
+		};
+
+		pmu_for_each_sys_event(metricgroup__sys_event_iter, &data);
+	}
+
 	if (metricgroups && !raw)
 		printf("\nMetric Groups:\n\n");
 	else if (metrics && !raw)
-- 
2.26.2


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[PATCH RFC v4 12/13] perf metricgroup: Support adding metrics for system PMUs

[John Garry]

Currently adding metrics for core- or uncore-based events matched by CPUID
is supported.

Extend this for system events.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 tools/perf/util/metricgroup.c | 59 +++++++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 3 deletions(-)

diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index 03f811eb600b..212b011240e5 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -413,6 +413,12 @@ static bool match_metric(const char *n, const char *list)
 	return false;
 }
 
+static bool match_pe_metric(struct pmu_event *pe, const char *metric)
+{
+	return match_metric(pe->metric_group, metric) ||
+	       match_metric(pe->metric_name, metric);
+}
+
 struct mep {
 	struct rb_node nd;
 	const char *name;
@@ -753,6 +759,16 @@ int __weak arch_get_runtimeparam(void)
 	return 1;
 }
 
+struct metricgroup_add_iter_data {
+	struct list_head *metric_list;
+	const char *metric;
+	struct metric **m;
+	bool metric_no_group;
+	struct expr_ids *ids;
+	bool *has_match;
+	int *ret;
+};
+
 static int __add_metric(struct list_head *metric_list,
 			struct pmu_event *pe,
 			bool metric_no_group,
@@ -863,7 +879,7 @@ static int __add_metric(struct list_head *metric_list,
 }
 
 #define map_for_each_event(__pe, __idx, __map)				\
-	for (__idx = 0, __pe = &__map->table[__idx];			\
+	if (__map) for (__idx = 0, __pe = &__map->table[__idx];		\
 	     __pe->name || __pe->metric_group || __pe->metric_name;	\
 	     __pe = &__map->table[++__idx])
 
@@ -1033,6 +1049,29 @@ static int add_metric(struct list_head *metric_list,
 	return ret;
 }
 
+static int metricgroup__add_metric_sys_event_iter(struct pmu_event *pe,
+						  void *data)
+{
+	struct metricgroup_add_iter_data *d = data;
+	int ret;
+
+	if (!match_pe_metric(pe, d->metric))
+		return 0;
+
+	ret = add_metric(d->metric_list, pe, d->metric_no_group, d->m, NULL, d->ids);
+	if (ret)
+		return ret;
+
+	ret = resolve_metric(d->metric_no_group,
+				     d->metric_list, NULL, d->ids);
+	if (ret)
+		return ret;
+
+	*(d->has_match) = true;
+
+	return *d->ret;
+}
+
 static int metricgroup__add_metric(const char *metric, bool metric_no_group,
 				   struct strbuf *events,
 				   struct list_head *metric_list,
@@ -1063,6 +1102,22 @@ static int metricgroup__add_metric(const char *metric, bool metric_no_group,
 			goto out;
 	}
 
+	{
+		struct metricgroup_iter_data data = {
+			.fn = metricgroup__add_metric_sys_event_iter,
+			.data = (void *) &(struct metricgroup_add_iter_data) {
+				.metric_list = &list,
+				.metric = metric,
+				.metric_no_group = metric_no_group,
+				.m = &m,
+				.ids = &ids,
+				.has_match = &has_match,
+				.ret = &ret,
+			},
+		};
+
+		pmu_for_each_sys_event(metricgroup__sys_event_iter, &data);
+	}
 	/* End of pmu events. */
 	if (!has_match) {
 		ret = -EINVAL;
@@ -1189,8 +1244,6 @@ int metricgroup__parse_groups(const struct option *opt,
 	struct evlist *perf_evlist = *(struct evlist **)opt->value;
 	struct pmu_events_map *map = perf_pmu__find_map(NULL);
 
-	if (!map)
-		return 0;
 
 	return parse_groups(perf_evlist, str, metric_no_group,
 			    metric_no_merge, NULL, metric_events, map);
-- 
2.26.2


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[PATCH RFC v4 13/13] perf vendor events: Add JSON metrics for imx8mm DDR Perf

[John Garry]

From: Joakim Zhang <qiangqing.zhang@nxp.com>

Add JSON metrics for imx8mm DDR Perf.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arch/arm64/freescale/imx8mm/sys/ddrc.json | 39 +++++++++++++++++++
 .../arm64/freescale/imx8mm/sys/metrics.json   | 18 +++++++++
 tools/perf/pmu-events/jevents.c               |  1 +
 3 files changed, 58 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json

diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
new file mode 100644
index 000000000000..3404a880542d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
@@ -0,0 +1,39 @@
+[
+   {
+           "BriefDescription": "ddr cycles event",
+           "EventCode": "0x00",
+           "EventName": "imx8_ddr.cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MM"
+   },
+   {
+           "BriefDescription": "ddr read-cycles event",
+           "EventCode": "0x2a",
+           "EventName": "imx8_ddr.read_cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MM"
+   },
+   {
+           "BriefDescription": "ddr write-cycles event",
+           "EventCode": "0x2b",
+           "EventName": "imx8_ddr.write_cycles",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MM"
+   },
+   {
+           "BriefDescription": "ddr read event",
+           "EventCode": "0x35",
+           "EventName": "imx8_ddr.read",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MM"
+   },
+   {
+           "BriefDescription": "ddr write event",
+           "EventCode": "0x38",
+           "EventName": "imx8_ddr.write",
+           "Unit": "imx8_ddr",
+           "Compat": "i.MX8MM"
+   }
+]
+
+
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
new file mode 100644
index 000000000000..ec00212336de
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
@@ -0,0 +1,18 @@
+[
+   {
+	    "BriefDescription": "bytes all masters read from ddr based on read-cycles event",
+	    "MetricName": "imx8mm_ddr_read.all",
+	    "MetricExpr": "imx8_ddr.read_cycles * 4 * 4",
+	    "ScaleUnit": "9.765625e-KB",
+	    "Unit": "imx8_ddr",
+	    "Compat": "i.MX8MM"
+    },
+   {
+	    "BriefDescription": "bytes all masters write to ddr based on write-cycles event",
+	    "MetricName": "imx8mm_ddr_write.all",
+	    "MetricExpr": "imx8_ddr.write_cycles * 4 * 4",
+	    "ScaleUnit": "9.765625e-4KB",
+	    "Unit": "imx8_ddr",
+	    "Compat": "i.MX8MM"
+    }
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 2e581bd9b0a6..b4bd48b076fd 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -257,6 +257,7 @@ static struct map {
 	{ "hisi_sccl,hha", "hisi_sccl,hha" },
 	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
 	/* it's not realistic to keep adding these, we need something more scalable ... */
+	{ "imx8_ddr", "imx8_ddr" },
 	{ "smmuv3_pmcg", "smmuv3_pmcg" },
 	{ "L3PMC", "amd_l3" },
 	{}
-- 
2.26.2


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Re: [PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[kajoljain]

On 10/8/20 3:45 PM, John Garry wrote:
> Currently event aliasing and metrics for only CPU and uncore PMUs is
> supported. In fact, only uncore PMUs aliasing is supported for when the
> uncore PMUs are fixed for a CPU, which may not always be the case for
> certain architectures.
> 
> This series adds support for PMU event aliasing and metrics for system and
> other uncore PMUs which are not tied to a specific CPU.
> 
> For this, we introduce system event tables in generated pmu-events.c,
> which contain a per-SoC table of events of all its system PMUs. Each
> per-PMU event is matched by a "COMPAT" property.
> 
> When creating aliased and metrics PMUs, we treat core/uncore and
> system PMUs differently:
> 
> - For CPU PMUs, we always match for the event mapfile based on the CPUID.
>   This has not changed.
> 
> - For an system PMUs, we iterate through all the events in all the system
>   PMU tables.
> 
>   Matches are based on the "COMPAT" property matching the PMU sysfs
>   identifier contents, in /sys/bus/event_source/devices/<PMU>/identifier
> 
>   Uncore PMUs, may be matched via CPUID or same as system PMU, depending
>   on whether the uncore PMU is tied to a specific CPUID.
> 
> Initial reference support is also added for ARM SMMUv3 PMCG (Performance
> Monitor Event Group) PMU for HiSilicon hip09 platform with only a single
> event so far - see driver in drivers/perf/arm_smmuv3_pmu.c reference.
> 
> Here is a sample output with this series on Huawei D06CS board:
> 
> root@ubuntu:/# ./perf list
>    [...]
> 
> smmu v3 pmcg:
>    smmuv3_pmcg.config_cache_miss
>         [Configuration cache miss caused by transaction or(ATS or
>         non-ATS)translation request. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.config_struct_access
>         [Configuration structure access. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.cycles
>         [Clock cycles. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.l1_tlb
>         [SMMUv3 PMCG L1 TABLE transation. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.pcie_ats_trans_passed
>         [PCIe ATS Translated Transaction passed through SMMU. Unit: 
> smmuv3_pmcg]
>    smmuv3_pmcg.pcie_ats_trans_rq
>         [PCIe ATS Translation Request received. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.tlb_miss
>         [TLB miss caused by incomingtransaction or (ATS or non-ATS) 
> translation request. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.trans_table_walk_access
>         [Translation table walk access. Unit: smmuv3_pmcg]
>    smmuv3_pmcg.transaction
>         [Transaction. Unit: smmuv3_pmcg]
> 
> 
> root@ubuntu:/# ./perf stat -v -e smmuv3_pmcg.l1_tlb sleep 1
> Using CPUID 0x00000000480fd010
> Using SYSID HIP08
> -> smmuv3_pmcg_200100020/event=0x8a/
> -> smmuv3_pmcg_200140020/event=0x8a/
> -> smmuv3_pmcg_100020/event=0x8a/
> -> smmuv3_pmcg_140020/event=0x8a/
> -> smmuv3_pmcg_200148020/event=0x8a/
> -> smmuv3_pmcg_148020/event=0x8a/
> smmuv3_pmcg.l1_tlb: 0 1001221690 1001221690
> smmuv3_pmcg.l1_tlb: 0 1001220090 1001220090
> smmuv3_pmcg.l1_tlb: 101 1001219660 1001219660
> smmuv3_pmcg.l1_tlb: 0 1001219010 1001219010
> smmuv3_pmcg.l1_tlb: 0 1001218360 1001218360
> smmuv3_pmcg.l1_tlb: 134 1001217850 1001217850
> 
> Performance counter stats for 'system wide':
> 
>                 235      smmuv3_pmcg.l1_tlb 
> 
>         1.001263128 seconds time elapsed
> 
> root@ubuntu:/#
> 
> Support is also added for imx8mm DDR PMU and HiSilicon hip09 uncore events.
> Some events for hip09 may not be accurate at the moment.
> 
> Series is here:
> https://github.com/hisilicon/kernel-dev/tree/private-topic-perf-5.9-sys-pmu-events-v4
> 
> Kernel part is here:
> https://lore.kernel.org/lkml/1602149181-237415-1-git-send-email-john.garry@huawei.com/T/#mc34f758ab72f3d4a90d854b9bda7e6bbb90835b2
> 
> Differences to v3:
> - Rebase to v5.9-rc7
> - Includes Ian's uncore metric expressions Fix and another fix
> - Add hip09 uncore events
> - Tidy jevents.c changes a bit
> 
> Differences to v2:
> - fixups for imx8mm JSONs
> - fix for metrics being repeated per PMU
> - use sysfs__read_str()
> - fix typo in PMCG JSON
> - drop evsel fix, which someone else fixed
> 
> Differences to v1:
> - Stop using SoC id and use a per-PMU identifier instead
> - Add metric group sys events support
>    - This is a bit hacky
> - Add imx8mm DDR Perf support
> - Add fix for parse events sel
> 	- without it, I get this spewed for metric event:
> 
> 	assertion failed at util/parse-events.c:1637
> 
> Ian Rogers (1):
>   perf metricgroup: Fix uncore metric expressions
> 
> Joakim Zhang (1):
>   perf vendor events: Add JSON metrics for imx8mm DDR Perf
> 
> John Garry (11):
>   perf jevents: Add support for an extra directory level
>   perf jevents: Add support for system events tables
>   perf pmu: Add pmu_id()
>   perf pmu: Add pmu_add_sys_aliases()
>   perf vendor events arm64: Add Architected events smmuv3-pmcg.json
>   perf vendor events arm64: Add hip09 SMMUv3 PMCG events
>   perf vendor events arm64: Add hip09 uncore events
>   perf metricgroup: Hack a fix for aliases when covering multiple PMUs
>   perf metricgroup: Split up metricgroup__print()
>   perf metricgroup: Support printing metric groups for system PMUs
>   perf metricgroup: Support adding metrics for system PMUs
> 

Hi John,
  I am looking into these patches, it seems they are not re-based on top of
latest Arnaldo's perf/core branch. Can you rebase these changes. I think we are missing
multiple updates.


Thanks,
Kajol Jain

>  .../arch/arm64/freescale/imx8mm/sys/ddrc.json |  39 +++
>  .../arm64/freescale/imx8mm/sys/metrics.json   |  18 +
>  .../hisilicon/hip09/sys/smmu-v3-pmcg.json     |  42 +++
>  .../hisilicon/hip09/sys/uncore-ddrc.json      |  58 ++++
>  .../arm64/hisilicon/hip09/sys/uncore-hha.json |  82 +++++
>  .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 106 ++++++
>  .../pmu-events/arch/arm64/smmuv3-pmcg.json    |  58 ++++
>  tools/perf/pmu-events/jevents.c               | 136 ++++++--
>  tools/perf/pmu-events/jevents.h               |  11 +-
>  tools/perf/pmu-events/pmu-events.h            |   6 +
>  tools/perf/util/metricgroup.c                 | 322 +++++++++++++-----
>  tools/perf/util/pmu.c                         |  96 ++++++
>  tools/perf/util/pmu.h                         |   3 +
>  13 files changed, 863 insertions(+), 114 deletions(-)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json
>  create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json
> 

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Re: [PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[John Garry]

On 08/10/2020 12:27, kajoljain wrote:
> Hi John,
>    I am looking into these patches, it seems they are not re-based on top of
> latest Arnaldo's perf/core branch. Can you rebase these changes. I think we are missing
> multiple updates.
> 
> 
> Thanks,
> Kajol Jain
> 

Hi Kajol Jain,

My thought was that since the kernel part needs acceptance first [0], 
which is based on v5.9-rc7, I would just use the same baseline here.

However I suppose I should still use Arnaldo's perf/core from now on as 
baseline, so I'll look at that now.

Thanks,
John

[0] 
https://lore.kernel.org/lkml/1602149181-237415-1-git-send-email-john.garry@huawei.com/T/#mc34f758ab72f3d4a90d854b9bda7e6bbb90835b2

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RE: [PATCH RFC v4 13/13] perf vendor events: Add JSON metrics for imx8mm DDR Perf

[Joakim Zhang]

> -----Original Message-----
> From: John Garry <john.garry@huawei.com>
> Sent: 2020年10月8日 18:15
> To: acme@kernel.org; will@kernel.org; mark.rutland@arm.com;
> jolsa@redhat.com; irogers@google.com; leo.yan@linaro.org;
> peterz@infradead.org; mingo@redhat.com;
> alexander.shishkin@linux.intel.com; namhyung@kernel.org;
> mathieu.poirier@linaro.org
> Cc: linuxarm@huawei.com; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; Joakim Zhang
> <qiangqing.zhang@nxp.com>; zhangshaokun@hisilicon.com;
> james.clark@arm.com; dl-linux-imx <linux-imx@nxp.com>; John Garry
> <john.garry@huawei.com>
> Subject: [PATCH RFC v4 13/13] perf vendor events: Add JSON metrics for
> imx8mm DDR Perf
> 
> From: Joakim Zhang <qiangqing.zhang@nxp.com>
> 
> Add JSON metrics for imx8mm DDR Perf.
> 
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
>  .../arch/arm64/freescale/imx8mm/sys/ddrc.json | 39 +++++++++++++++++++
>  .../arm64/freescale/imx8mm/sys/metrics.json   | 18 +++++++++
>  tools/perf/pmu-events/jevents.c               |  1 +
>  3 files changed, 58 insertions(+)
>  create mode 100644
> tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
>  create mode 100644
> tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
> 
> diff --git
> a/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
> b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
> new file mode 100644
> index 000000000000..3404a880542d
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
> @@ -0,0 +1,39 @@
> +[
> +   {
> +           "BriefDescription": "ddr cycles event",
> +           "EventCode": "0x00",
> +           "EventName": "imx8_ddr.cycles",
Could you help change to imx8mm_ddr.cycles? Thanks a lot!

> +           "Unit": "imx8_ddr",
> +           "Compat": "i.MX8MM"
> +   },
> +   {
> +           "BriefDescription": "ddr read-cycles event",
> +           "EventCode": "0x2a",
> +           "EventName": "imx8_ddr.read_cycles",
Same here.

> +           "Unit": "imx8_ddr",
> +           "Compat": "i.MX8MM"
> +   },
> +   {
> +           "BriefDescription": "ddr write-cycles event",
> +           "EventCode": "0x2b",
> +           "EventName": "imx8_ddr.write_cycles",
Same here.

> +           "Unit": "imx8_ddr",
> +           "Compat": "i.MX8MM"
> +   },
> +   {
> +           "BriefDescription": "ddr read event",
> +           "EventCode": "0x35",
> +           "EventName": "imx8_ddr.read",
Same here.

> +           "Unit": "imx8_ddr",
> +           "Compat": "i.MX8MM"
> +   },
> +   {
> +           "BriefDescription": "ddr write event",
> +           "EventCode": "0x38",
> +           "EventName": "imx8_ddr.write",
Same here.

> +           "Unit": "imx8_ddr",
> +           "Compat": "i.MX8MM"
> +   }
> +]
> +
> +
> diff --git
> a/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
> b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
> new file mode 100644
> index 000000000000..ec00212336de
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json
> @@ -0,0 +1,18 @@
> +[
> +   {
> +	    "BriefDescription": "bytes all masters read from ddr based on
> read-cycles event",
> +	    "MetricName": "imx8mm_ddr_read.all",
> +	    "MetricExpr": "imx8_ddr.read_cycles * 4 * 4",
> +	    "ScaleUnit": "9.765625e-KB",

A typo, should be "ScaleUnit": "9.765625e-4KB".

Best Regards,
Joakim Zhang
> +	    "Unit": "imx8_ddr",
> +	    "Compat": "i.MX8MM"
> +    },
> +   {
> +	    "BriefDescription": "bytes all masters write to ddr based on
> write-cycles event",
> +	    "MetricName": "imx8mm_ddr_write.all",
> +	    "MetricExpr": "imx8_ddr.write_cycles * 4 * 4",
> +	    "ScaleUnit": "9.765625e-4KB",
> +	    "Unit": "imx8_ddr",
> +	    "Compat": "i.MX8MM"
> +    }
> +]
> diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
> index 2e581bd9b0a6..b4bd48b076fd 100644
> --- a/tools/perf/pmu-events/jevents.c
> +++ b/tools/perf/pmu-events/jevents.c
> @@ -257,6 +257,7 @@ static struct map {
>  	{ "hisi_sccl,hha", "hisi_sccl,hha" },
>  	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
>  	/* it's not realistic to keep adding these, we need something more
> scalable ... */
> +	{ "imx8_ddr", "imx8_ddr" },
>  	{ "smmuv3_pmcg", "smmuv3_pmcg" },
>  	{ "L3PMC", "amd_l3" },
>  	{}
> --
> 2.26.2

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Re: [PATCH RFC v4 13/13] perf vendor events: Add JSON metrics for imx8mm DDR Perf

[John Garry]

On 12/10/2020 11:03, Joakim Zhang wrote:
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
>> @@ -0,0 +1,39 @@
>> +[
>> +   {
>> +           "BriefDescription": "ddr cycles event",
>> +           "EventCode": "0x00",
>> +           "EventName": "imx8_ddr.cycles",
> Could you help change to imx8mm_ddr.cycles? Thanks a lot!

Can do.

Note that I want to improve perf list in future such that alias 
"imx8_ddr.cycles" removes kernel PMU events which this alias is 
matching. The motivation is that perf list can be swamped by kernel 
uncore PMU events listing.

> 
>> +           "Unit": "imx8_ddr",
>> +           "Compat": "i.MX8MM"


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Re: [PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[Jiri Olsa]

On Thu, Oct 08, 2020 at 12:49:15PM +0100, John Garry wrote:
> On 08/10/2020 12:27, kajoljain wrote:
> > Hi John,
> >    I am looking into these patches, it seems they are not re-based on top of
> > latest Arnaldo's perf/core branch. Can you rebase these changes. I think we are missing
> > multiple updates.
> > 
> > 
> > Thanks,
> > Kajol Jain
> > 
> 
> Hi Kajol Jain,
> 
> My thought was that since the kernel part needs acceptance first [0], which
> is based on v5.9-rc7, I would just use the same baseline here.
> 
> However I suppose I should still use Arnaldo's perf/core from now on as
> baseline, so I'll look at that now.

yes please, I can't already apply 2nd patch..

	patching file pmu-events/jevents.c
	Hunk #1 succeeded at 82 with fuzz 2 (offset 29 lines).
	Hunk #2 FAILED at 335.
	Hunk #3 FAILED at 354.
	Hunk #4 succeeded at 406 (offset 22 lines).
	Hunk #5 FAILED at 439.
	Hunk #6 FAILED at 531.
	Hunk #7 FAILED at 555.
	Hunk #8 FAILED at 602.
	Hunk #9 FAILED at 698.
	Hunk #10 succeeded at 770 (offset 2 lines).
	Hunk #11 succeeded at 813 (offset 2 lines).
	Hunk #12 succeeded at 1075 (offset 2 lines).
	Hunk #13 succeeded at 1242 (offset 2 lines).
	Hunk #14 succeeded at 1273 (offset 2 lines).
	7 out of 14 hunks FAILED -- saving rejects to file pmu-events/jevents.c.rej
	can't find file to patch at input line 439
thanks,
jirka


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Re: [PATCH RFC v4 00/13] perf pmu-events: Support event aliasing for system PMUs

[John Garry]

On 14/10/2020 12:16, Jiri Olsa wrote:
>> My thought was that since the kernel part needs acceptance first [0], which
>> is based on v5.9-rc7, I would just use the same baseline here.
>>
>> However I suppose I should still use Arnaldo's perf/core from now on as
>> baseline, so I'll look at that now.
> yes please, I can't already apply 2nd patch..
> 
> 	patching file pmu-events/jevents.c
> 	Hunk #1 succeeded at 82 with fuzz 2 (offset 29 lines).
> 	Hunk #2 FAILED at 335.
> 	Hunk #3 FAILED at 354.
> 	Hunk #4 succeeded at 406 (offset 22 lines).
> 	Hunk #5 FAILED at 439.
> 	Hunk #6 FAILED at 531.
> 	Hunk #7 FAILED at 555.
> 	Hunk #8 FAILED at 602.
> 	Hunk #9 FAILED at 698.
> 	Hunk #10 succeeded at 770 (offset 2 lines).
> 	Hunk #11 succeeded at 813 (offset 2 lines).
> 	Hunk #12 succeeded at 1075 (offset 2 lines).
> 	Hunk #13 succeeded at 1242 (offset 2 lines).
> 	Hunk #14 succeeded at 1273 (offset 2 lines).
> 	7 out of 14 hunks FAILED -- saving rejects to file pmu-events/jevents.c.rej
> 	can't find file to patch at input line 439

OK, so I already did the rebase and it was quite straightforward - the 
conflicts came with the recent changes in jevents.

I will send out soon.

Thanks,
John

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Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

[Robin Murphy]

On 2020-10-08 11:15, John Garry wrote:
> Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
> platform.
> 
> This contains a mix of architected and IMP def events
> 
> Signed-off-by: John Garry <john.garry@huawei.com>
> ---
>   .../hisilicon/hip09/sys/smmu-v3-pmcg.json     | 42 +++++++++++++++++++
>   1 file changed, 42 insertions(+)
>   create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
> new file mode 100644
> index 000000000000..8abafbb2dcb4
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
> @@ -0,0 +1,42 @@
> +[
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.CYCLES"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
> +	    "Compat": "0x00030736"
> +   },
> +   {
> +	    "EventCode": "0x8a",
> +	    "EventName": "smmuv3_pmcg.L1_TLB",
> +	    "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
> +	    "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",

Those typos are either missing "c"s or "l"s, but with SMMU it's never 
clear which ;)

Robin.

> +	    "Unit": "smmuv3_pmcg",
> +	    "Compat": "0x00030736"
> +   },
> +]
> 

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Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

[John Garry]

On 14/10/2020 19:06, Robin Murphy wrote:
>>
>> +        "EventCode": "0x8a",
>> +        "EventName": "smmuv3_pmcg.L1_TLB",
>> +        "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
>> +        "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",
> 
> Those typos are either missing "c"s or "l"s, but with SMMU it's never 
> clear which ;)

Ha, I think either could work in this case.

The actual electronic translation I got is "command received by the L1 
TLB", so I'll stick with that until someone here wants to expand on that.

Cheers

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Ian Rogers]

On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
>
> Greeting,
>
> FYI, we noticed the following commit (built with gcc-9):
>
> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when covering multiple PMUs")
> url: https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049
>
>
> in testcase: perf-sanity-tests
> version: perf-x86_64-c85fb28b6f99-1_20201008
> with following parameters:
>
>         perf_compiler: gcc
>         ucode: 0xdc
>
>
>
> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
>
> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):

I believe this is a Skylake and there is a known bug in the Skylake
metric DRAM_Parallel_Reads as described here:
https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
Fixing the bug needs more knowledge than what is available in manuals.
Hopefully Intel can take a look.

Thanks,
Ian

>
>
> If you fix the issue, kindly add following tag
> Reported-by: kernel test robot <rong.a.chen@intel.com>
>
>
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 67
> 67: Parse and process metrics                             : FAILED!
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 68
> 68: x86 rdpmc                                             : Ok
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 69
> 69: Convert perf time to TSC                              : Ok
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 70
> 70: DWARF unwind                                          : Ok
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 71
> 71: x86 instruction decoder - new instructions            : Ok
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 72
> 72: Intel PT packet decoder                               : Ok
> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 73
> 73: x86 bp modify                                         : Ok
> 2020-10-16 19:31:53 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 74
> 74: probe libc's inet_pton & backtrace it with ping       : Ok
> 2020-10-16 19:31:54 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 75
> 75: Zstd perf.data compression/decompression              : Ok
>
>
>
> To reproduce:
>
>         git clone https://github.com/intel/lkp-tests.git
>         cd lkp-tests
>         bin/lkp install job.yaml  # job file is attached in this email
>         bin/lkp run     job.yaml
>
>
>
> Thanks,
> Rong Chen
>

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Andi Kleen]

> I believe this is a Skylake and there is a known bug in the Skylake
> metric DRAM_Parallel_Reads as described here:
> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
> Fixing the bug needs more knowledge than what is available in manuals.
> Hopefully Intel can take a look.

Oh I missed the original mail for some reason.  Yes it should be cmask instead of thresh
for client.  I think thresh is used on the server uncore only, not on the client.

Jin Yao, can you send a patch please?

-Andi


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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Jin, Yao]

On 10/19/2020 9:52 AM, Andi Kleen wrote:
>> I believe this is a Skylake and there is a known bug in the Skylake
>> metric DRAM_Parallel_Reads as described here:
>> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
>> Fixing the bug needs more knowledge than what is available in manuals.
>> Hopefully Intel can take a look.
> 
> Oh I missed the original mail for some reason.  Yes it should be cmask instead of thresh
> for client.  I think thresh is used on the server uncore only, not on the client.
> 
> Jin Yao, can you send a patch please?
> 
> -Andi
> 

Yes, the DRAM_Parallel_Reads works on server but it's failed on client.

I will post a patch to fix that.

Thanks
Jin Yao


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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[John Garry]

On 19/10/2020 00:30, Ian Rogers wrote:
> On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
>>
>> Greeting,
>>
>> FYI, we noticed the following commit (built with gcc-9):
>>
>> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when covering multiple PMUs")
>> url: https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049
>>
>>
>> in testcase: perf-sanity-tests
>> version: perf-x86_64-c85fb28b6f99-1_20201008
>> with following parameters:
>>
>>          perf_compiler: gcc
>>          ucode: 0xdc
>>
>>
>>
>> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
>>
>> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):
> 
> I believe this is a Skylake and there is a known bug in the Skylake
> metric DRAM_Parallel_Reads as described here:
> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
> Fixing the bug needs more knowledge than what is available in manuals.
> Hopefully Intel can take a look.
> 
> Thanks,
> Ian

So this named patch ("perf metricgroup: Hack a fix for aliases...") is 
breaking test #67 on my machine also, which is a broadwell.

I will have a look, but I was hoping that Ian would have a proper fix 
for this on top of ("perf metricgroup: Fix uncore metric expressions"), 
which now looks to be merged.

Thanks!

> 
>>
>>
>> If you fix the issue, kindly add following tag
>> Reported-by: kernel test robot <rong.a.chen@intel.com>
>>
>>
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 67
>> 67: Parse and process metrics                             : FAILED!
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 68
>> 68: x86 rdpmc                                             : Ok
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 69
>> 69: Convert perf time to TSC                              : Ok
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 70
>> 70: DWARF unwind                                          : Ok
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 71
>> 71: x86 instruction decoder - new instructions            : Ok
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 72
>> 72: Intel PT packet decoder                               : Ok
>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 73
>> 73: x86 bp modify                                         : Ok
>> 2020-10-16 19:31:53 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 74
>> 74: probe libc's inet_pton & backtrace it with ping       : Ok
>> 2020-10-16 19:31:54 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 75
>> 75: Zstd perf.data compression/decompression              : Ok
>>
>>
>>
>> To reproduce:
>>
>>          git clone https://github.com/intel/lkp-tests.git
>>          cd lkp-tests
>>          bin/lkp install job.yaml  # job file is attached in this email
>>          bin/lkp run     job.yaml
>>
>>
>>
>> Thanks,
>> Rong Chen
>>
> .
> 


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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Jin, Yao]

Hi Garry, Hi Ian,

On 10/19/2020 5:48 PM, John Garry wrote:
> On 19/10/2020 00:30, Ian Rogers wrote:
>> On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
>>>
>>> Greeting,
>>>
>>> FYI, we noticed the following commit (built with gcc-9):
>>>
>>> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when 
>>> covering multiple PMUs")
>>> url: 
>>> https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049 
>>>
>>>
>>>
>>> in testcase: perf-sanity-tests
>>> version: perf-x86_64-c85fb28b6f99-1_20201008
>>> with following parameters:
>>>
>>>          perf_compiler: gcc
>>>          ucode: 0xdc
>>>
>>>
>>>
>>> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
>>>
>>> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):
>>
>> I believe this is a Skylake and there is a known bug in the Skylake
>> metric DRAM_Parallel_Reads as described here:
>> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
>> Fixing the bug needs more knowledge than what is available in manuals.
>> Hopefully Intel can take a look.
>>
>> Thanks,
>> Ian
> 
> So this named patch ("perf metricgroup: Hack a fix for aliases...") is breaking test #67 on my 
> machine also, which is a broadwell.
> 
> I will have a look, but I was hoping that Ian would have a proper fix for this on top of ("perf 
> metricgroup: Fix uncore metric expressions"), which now looks to be merged.
> 
> Thanks!
> 

I just think they are different issues.

On my KBL client, the perf test #67 is passed.

But DRAM_Parallel_Reads does have issue.

root@kbl-ppc:~# perf stat -M DRAM_Parallel_Reads -- sleep 1
event syntax error: '{arb/event=0x80,umask=0x2/,arb/event=0x80,umask=0x2,thresh=1/}:W'
                      \___ unknown term 'thresh' for pmu 'uncore_arb'

valid terms: event,edge,inv,umask,cmask,config,config1,config2,name,period,percore

Initial error:
event syntax error: '..umask=0x2/,arb/event=0x80,umask=0x2,thresh=1/}:W'
                                   \___ Cannot find PMU `arb'. Missing kernel support?

  Usage: perf stat [<options>] [<command>]

     -M, --metrics <metric/metric group list>
                           monitor specified metrics or metric groups (separated by ,)

I have a patch to fix DRAM_Parallel_Reads.

After:

root@kbl-ppc:~# perf stat -M MEM_Parallel_Reads -- sleep 1

  Performance counter stats for 'system wide':

          3,043,952      arb/event=0x80,umask=0x2/ #     1.00 MEM_Parallel_Reads

        1.000879932 seconds time elapsed

I will post the patch later.

Thanks
Jin Yao

>>
>>>
>>>
>>> If you fix the issue, kindly add following tag
>>> Reported-by: kernel test robot <rong.a.chen@intel.com>
>>>
>>>
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 67
>>> 67: Parse and process metrics                             : FAILED!
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 68
>>> 68: x86 rdpmc                                             : Ok
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 69
>>> 69: Convert perf time to TSC                              : Ok
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 70
>>> 70: DWARF unwind                                          : Ok
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 71
>>> 71: x86 instruction decoder - new instructions            : Ok
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 72
>>> 72: Intel PT packet decoder                               : Ok
>>> 2020-10-16 19:31:52 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 73
>>> 73: x86 bp modify                                         : Ok
>>> 2020-10-16 19:31:53 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 74
>>> 74: probe libc's inet_pton & backtrace it with ping       : Ok
>>> 2020-10-16 19:31:54 sudo 
>>> /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf 
>>> test 75
>>> 75: Zstd perf.data compression/decompression              : Ok
>>>
>>>
>>>
>>> To reproduce:
>>>
>>>          git clone https://github.com/intel/lkp-tests.git
>>>          cd lkp-tests
>>>          bin/lkp install job.yaml  # job file is attached in this email
>>>          bin/lkp run     job.yaml
>>>
>>>
>>>
>>> Thanks,
>>> Rong Chen
>>>
>> .
>>
> 

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Ian Rogers]

On Mon, Oct 19, 2020 at 2:51 AM John Garry <john.garry@huawei.com> wrote:
>
> On 19/10/2020 00:30, Ian Rogers wrote:
> > On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
> >>
> >> Greeting,
> >>
> >> FYI, we noticed the following commit (built with gcc-9):
> >>
> >> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when covering multiple PMUs")
> >> url: https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049
> >>
> >>
> >> in testcase: perf-sanity-tests
> >> version: perf-x86_64-c85fb28b6f99-1_20201008
> >> with following parameters:
> >>
> >>          perf_compiler: gcc
> >>          ucode: 0xdc
> >>
> >>
> >>
> >> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
> >>
> >> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):
> >
> > I believe this is a Skylake and there is a known bug in the Skylake
> > metric DRAM_Parallel_Reads as described here:
> > https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
> > Fixing the bug needs more knowledge than what is available in manuals.
> > Hopefully Intel can take a look.
> >
> > Thanks,
> > Ian
>
> So this named patch ("perf metricgroup: Hack a fix for aliases...") is
> breaking test #67 on my machine also, which is a broadwell.

Thanks for taking a look John. If you want help you can send the
output of "perf test 67 -vvv" to me. It is possible Broadwell has
similar glitches in the json to Skylake. I tested the original test on
server parts as I can access them as cloud machines.

> I will have a look, but I was hoping that Ian would have a proper fix
> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
> which now looks to be merged.

I still have these changes to look at in my inbox but I'm assuming
they're good :-) Sorry for not getting to them, but it's good they are
merged.

Thanks,
Ian

> Thanks!
>
> >
> >>
> >>
> >> If you fix the issue, kindly add following tag
> >> Reported-by: kernel test robot <rong.a.chen@intel.com>
> >>
> >>
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 67
> >> 67: Parse and process metrics                             : FAILED!
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 68
> >> 68: x86 rdpmc                                             : Ok
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 69
> >> 69: Convert perf time to TSC                              : Ok
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 70
> >> 70: DWARF unwind                                          : Ok
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 71
> >> 71: x86 instruction decoder - new instructions            : Ok
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 72
> >> 72: Intel PT packet decoder                               : Ok
> >> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 73
> >> 73: x86 bp modify                                         : Ok
> >> 2020-10-16 19:31:53 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 74
> >> 74: probe libc's inet_pton & backtrace it with ping       : Ok
> >> 2020-10-16 19:31:54 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 75
> >> 75: Zstd perf.data compression/decompression              : Ok
> >>
> >>
> >>
> >> To reproduce:
> >>
> >>          git clone https://github.com/intel/lkp-tests.git
> >>          cd lkp-tests
> >>          bin/lkp install job.yaml  # job file is attached in this email
> >>          bin/lkp run     job.yaml
> >>
> >>
> >>
> >> Thanks,
> >> Rong Chen
> >>
> > .
> >
>

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[John Garry]

On 19/10/2020 17:20, Ian Rogers wrote:
>>> n
>> So this named patch ("perf metricgroup: Hack a fix for aliases...") is
>> breaking test #67 on my machine also, which is a broadwell.
> Thanks for taking a look John. If you want help you can send the
> output of "perf test 67 -vvv" to me. It is possible Broadwell has
> similar glitches in the json to Skylake. I tested the original test on
> server parts as I can access them as cloud machines.

Here it is:

john@localhost:~/kernel-dev7/tools/perf> ./perf test -vv 67
Couldn't bump rlimit(MEMLOCK), failures may take place when creating BPF 
maps, etc
67: Parse and process metrics                             :
--- start ---
test child forked, pid 24433
metric expr inst_retired.any / cpu_clk_unhalted.thread for IPC
parsing metric: inst_retired.any / cpu_clk_unhalted.thread
found event inst_retired.any
found event cpu_clk_unhalted.thread
adding {inst_retired.any,cpu_clk_unhalted.thread}:W
Attempting to add event pmu 'inst_retired.any' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'cpu_clk_unhalted.thread' with '' that may 
result in non-fatal errors
parsing metric: inst_retired.any / cpu_clk_unhalted.thread
lookup: is_ref 0, counted 0, val 300.000000: inst_retired.any
lookup: is_ref 0, counted 101, val 200.000000: cpu_clk_unhalted.thread
metric expr idq_uops_not_delivered.core / (4 * (( ( 
cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active 
/ cpu_clk_unhalted.ref_xclk ) ))) for Frontend_Bound_SMT
parsing metric: idq_uops_not_delivered.core / (4 * (( ( 
cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active 
/ cpu_clk_unhalted.ref_xclk ) )))
found event cpu_clk_unhalted.one_thread_active
found event cpu_clk_unhalted.ref_xclk
found event idq_uops_not_delivered.core
found event cpu_clk_unhalted.thread
adding 
{cpu_clk_unhalted.one_thread_active,cpu_clk_unhalted.ref_xclk,idq_uops_not_delivered.core,cpu_clk_unhalted.thread}:W
Attempting to add event pmu 'cpu_clk_unhalted.one_thread_active' with '' 
that may result in non-fatal errors
Attempting to add event pmu 'cpu_clk_unhalted.ref_xclk' with '' that may 
result in non-fatal errors
Attempting to add event pmu 'idq_uops_not_delivered.core' with '' that 
may result in non-fatal errors
Attempting to add event pmu 'cpu_clk_unhalted.thread' with '' that may 
result in non-fatal errors
parsing metric: idq_uops_not_delivered.core / (4 * (( ( 
cpu_clk_unhalted.thread / 2 ) * ( 1 + cpu_clk_unhalted.one_thread_active 
/ cpu_clk_unhalted.ref_xclk ) )))
lookup: is_ref 0, counted 46, val 300.000000: idq_uops_not_delivered.core
lookup: is_ref 0, counted 0, val 200.000000: cpu_clk_unhalted.thread
lookup: is_ref 0, counted 216, val 400.000000: 
cpu_clk_unhalted.one_thread_active
lookup: is_ref 0, counted 46, val 600.000000: cpu_clk_unhalted.ref_xclk
metric expr (dcache_miss_cpi + icache_miss_cycles) for cache_miss_cycles
parsing metric: (dcache_miss_cpi + icache_miss_cycles)
metric expr l1d\-loads\-misses / inst_retired.any for dcache_miss_cpi
parsing metric: l1d\-loads\-misses / inst_retired.any
metric expr l1i\-loads\-misses / inst_retired.any for icache_miss_cycles
parsing metric: l1i\-loads\-misses / inst_retired.any
found event inst_retired.any
found event l1i-loads-misses
found event l1d-loads-misses
adding {inst_retired.any,l1i-loads-misses,l1d-loads-misses}:W
Attempting to add event pmu 'inst_retired.any' with '' that may result 
in non-fatal errors
adding ref metric icache_miss_cycles: l1i\-loads\-misses / inst_retired.any
adding ref metric dcache_miss_cpi: l1d\-loads\-misses / inst_retired.any
parsing metric: (dcache_miss_cpi + icache_miss_cycles)
lookup: is_ref 1, counted 0, val 0.000000: dcache_miss_cpi
processing metric: dcache_miss_cpi ENTRY
parsing metric: l1d\-loads\-misses / inst_retired.any
lookup: is_ref 0, counted 105, val 300.000000: l1d-loads-misses
lookup: is_ref 0, counted 46, val 400.000000: inst_retired.any
processing metric: dcache_miss_cpi EXIT: 0.750000
lookup: is_ref 1, counted 0, val 0.000000: icache_miss_cycles
processing metric: icache_miss_cycles ENTRY
parsing metric: l1i\-loads\-misses / inst_retired.any
lookup: is_ref 0, counted 216, val 200.000000: l1i-loads-misses
lookup: is_ref 0, counted 46, val 400.000000: inst_retired.any
processing metric: icache_miss_cycles EXIT: 0.500000
metric expr d_ratio(dcache_l2_all_hits, dcache_l2_all) for DCache_L2_Hits
parsing metric: d_ratio(dcache_l2_all_hits, dcache_l2_all)
metric expr l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit for DCache_L2_All_Hits
parsing metric: l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit
metric expr dcache_l2_all_hits + dcache_l2_all_miss for DCache_L2_All
parsing metric: dcache_l2_all_hits + dcache_l2_all_miss
metric expr l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit for DCache_L2_All_Hits
parsing metric: l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit
metric expr max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss 
for DCache_L2_All_Miss
parsing metric: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
found event l2_rqsts.rfo_miss
found event l2_rqsts.pf_miss
found event l2_rqsts.rfo_hit
found event l2_rqsts.demand_data_rd_hit
found event l2_rqsts.all_demand_data_rd
found event l2_rqsts.pf_hit
adding 
{l2_rqsts.rfo_miss,l2_rqsts.pf_miss,l2_rqsts.rfo_hit,l2_rqsts.demand_data_rd_hit,l2_rqsts.all_demand_data_rd,l2_rqsts.pf_hit}:W
Attempting to add event pmu 'l2_rqsts.rfo_miss' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.pf_miss' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.rfo_hit' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.demand_data_rd_hit' with '' that 
may result in non-fatal errors
Attempting to add event pmu 'l2_rqsts.all_demand_data_rd' with '' that 
may result in non-fatal errors
Attempting to add event pmu 'l2_rqsts.pf_hit' with '' that may result in 
non-fatal errors
adding ref metric DCache_L2_All_Miss: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
adding ref metric DCache_L2_All_Hits: l2_rqsts.demand_data_rd_hit + 
l2_rqsts.pf_hit + l2_rqsts.rfo_hit
adding ref metric DCache_L2_All: dcache_l2_all_hits + dcache_l2_all_miss
adding ref metric DCache_L2_All_Hits: l2_rqsts.demand_data_rd_hit + 
l2_rqsts.pf_hit + l2_rqsts.rfo_hit
parsing metric: d_ratio(dcache_l2_all_hits, dcache_l2_all)
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all_hits
processing metric: dcache_l2_all_hits ENTRY
parsing metric: l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit
lookup: is_ref 0, counted 8, val 100.000000: l2_rqsts.demand_data_rd_hit
lookup: is_ref 0, counted 224, val 200.000000: l2_rqsts.pf_hit
lookup: is_ref 0, counted 46, val 300.000000: l2_rqsts.rfo_hit
processing metric: dcache_l2_all_hits EXIT: 600.000000
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all
processing metric: dcache_l2_all ENTRY
parsing metric: dcache_l2_all_hits + dcache_l2_all_miss
lookup: is_ref 1, counted 1, val 600.000000: dcache_l2_all_hits
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all_miss
processing metric: dcache_l2_all_miss ENTRY
parsing metric: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
lookup: is_ref 0, counted 112, val 400.000000: l2_rqsts.all_demand_data_rd
lookup: is_ref 0, counted 8, val 100.000000: l2_rqsts.demand_data_rd_hit
lookup: is_ref 0, counted 100, val 500.000000: l2_rqsts.pf_miss
lookup: is_ref 0, counted 120, val 600.000000: l2_rqsts.rfo_miss
processing metric: dcache_l2_all_miss EXIT: 1400.000000
processing metric: dcache_l2_all EXIT: 2000.000000
metric expr d_ratio(dcache_l2_all_miss, dcache_l2_all) for DCache_L2_Misses
parsing metric: d_ratio(dcache_l2_all_miss, dcache_l2_all)
metric expr max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss 
for DCache_L2_All_Miss
parsing metric: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
metric expr dcache_l2_all_hits + dcache_l2_all_miss for DCache_L2_All
parsing metric: dcache_l2_all_hits + dcache_l2_all_miss
metric expr l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit for DCache_L2_All_Hits
parsing metric: l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit
metric expr max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss 
for DCache_L2_All_Miss
parsing metric: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
found event l2_rqsts.rfo_miss
found event l2_rqsts.pf_miss
found event l2_rqsts.rfo_hit
found event l2_rqsts.demand_data_rd_hit
found event l2_rqsts.all_demand_data_rd
found event l2_rqsts.pf_hit
adding 
{l2_rqsts.rfo_miss,l2_rqsts.pf_miss,l2_rqsts.rfo_hit,l2_rqsts.demand_data_rd_hit,l2_rqsts.all_demand_data_rd,l2_rqsts.pf_hit}:W
Attempting to add event pmu 'l2_rqsts.rfo_miss' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.pf_miss' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.rfo_hit' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'l2_rqsts.demand_data_rd_hit' with '' that 
may result in non-fatal errors
Attempting to add event pmu 'l2_rqsts.all_demand_data_rd' with '' that 
may result in non-fatal errors
Attempting to add event pmu 'l2_rqsts.pf_hit' with '' that may result in 
non-fatal errors
adding ref metric DCache_L2_All_Miss: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
adding ref metric DCache_L2_All_Hits: l2_rqsts.demand_data_rd_hit + 
l2_rqsts.pf_hit + l2_rqsts.rfo_hit
adding ref metric DCache_L2_All: dcache_l2_all_hits + dcache_l2_all_miss
adding ref metric DCache_L2_All_Miss: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
parsing metric: d_ratio(dcache_l2_all_miss, dcache_l2_all)
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all_miss
processing metric: dcache_l2_all_miss ENTRY
parsing metric: max(l2_rqsts.all_demand_data_rd - 
l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss
lookup: is_ref 0, counted 128, val 400.000000: l2_rqsts.all_demand_data_rd
lookup: is_ref 0, counted 224, val 100.000000: l2_rqsts.demand_data_rd_hit
lookup: is_ref 0, counted 112, val 500.000000: l2_rqsts.pf_miss
lookup: is_ref 0, counted 0, val 600.000000: l2_rqsts.rfo_miss
processing metric: dcache_l2_all_miss EXIT: 1400.000000
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all
processing metric: dcache_l2_all ENTRY
parsing metric: dcache_l2_all_hits + dcache_l2_all_miss
lookup: is_ref 1, counted 0, val 0.000000: dcache_l2_all_hits
processing metric: dcache_l2_all_hits ENTRY
parsing metric: l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + 
l2_rqsts.rfo_hit
lookup: is_ref 0, counted 224, val 100.000000: l2_rqsts.demand_data_rd_hit
lookup: is_ref 0, counted 0, val 200.000000: l2_rqsts.pf_hit
lookup: is_ref 0, counted 152, val 300.000000: l2_rqsts.rfo_hit
processing metric: dcache_l2_all_hits EXIT: 600.000000
lookup: is_ref 1, counted 1, val 1400.000000: dcache_l2_all_miss
processing metric: dcache_l2_all EXIT: 2000.000000
metric expr ipc + m2 for M1
parsing metric: ipc + m2
metric expr ipc + m1 for M2
parsing metric: ipc + m1
metric expr ipc + m2 for M1
parsing metric: ipc + m2
failed: recursion detected for m2
metric expr 1/m3 for M3
parsing metric: 1/m3
metric expr 1/m3 for M3
parsing metric: 1/m3
failed: recursion detected for m3
metric expr inst_retired.any / cpu_clk_unhalted.thread for IPC
parsing metric: inst_retired.any / cpu_clk_unhalted.thread
metric expr (dcache_miss_cpi + icache_miss_cycles) for cache_miss_cycles
parsing metric: (dcache_miss_cpi + icache_miss_cycles)
metric expr l1d\-loads\-misses / inst_retired.any for dcache_miss_cpi
parsing metric: l1d\-loads\-misses / inst_retired.any
metric expr l1i\-loads\-misses / inst_retired.any for icache_miss_cycles
parsing metric: l1i\-loads\-misses / inst_retired.any
found event inst_retired.any
found event cpu_clk_unhalted.thread
found event inst_retired.any
found event l1i-loads-misses
found event l1d-loads-misses
adding 
{inst_retired.any,cpu_clk_unhalted.thread}:W,{inst_retired.any,l1i-loads-misses,l1d-loads-misses}:W
Attempting to add event pmu 'inst_retired.any' with '' that may result 
in non-fatal errors
Attempting to add event pmu 'cpu_clk_unhalted.thread' with '' that may 
result in non-fatal errors
Attempting to add event pmu 'inst_retired.any' with '' that may result 
in non-fatal errors
parsing metric: inst_retired.any / cpu_clk_unhalted.thread
lookup: is_ref 0, counted 64, val 800.000000: inst_retired.any
lookup: is_ref 0, counted 32, val 200.000000: cpu_clk_unhalted.thread
adding ref metric icache_miss_cycles: l1i\-loads\-misses / inst_retired.any
adding ref metric dcache_miss_cpi: l1d\-loads\-misses / inst_retired.any
parsing metric: (dcache_miss_cpi + icache_miss_cycles)
lookup: is_ref 1, counted 0, val 0.000000: dcache_miss_cpi
processing metric: dcache_miss_cpi ENTRY
parsing metric: l1d\-loads\-misses / inst_retired.any
lookup: is_ref 0, counted 0, val 300.000000: l1d-loads-misses
lookup: is_ref 0, counted 64, val 800.000000: inst_retired.any
processing metric: dcache_miss_cpi EXIT: 0.375000
lookup: is_ref 1, counted 0, val 0.000000: icache_miss_cycles
processing metric: icache_miss_cycles ENTRY
parsing metric: l1i\-loads\-misses / inst_retired.any
lookup: is_ref 0, counted 32, val 200.000000: l1i-loads-misses
lookup: is_ref 0, counted 64, val 800.000000: inst_retired.any
processing metric: icache_miss_cycles EXIT: 0.250000
FAILED tests/parse-metric.c:343 group IPC failed, wrong ratio
FAILED tests/parse-metric.c:357 test metric group
test child finished with -1
---- end ----
Parse and process metrics: FAILED!
john@localhost:~/kernel-dev7/tools/perf>


> 
>> I will have a look, but I was hoping that Ian would have a proper fix
>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
>> which now looks to be merged.
> I still have these changes to look at in my inbox but I'm assuming
> they're good:-) 

really? I wouldn't assume my hacky patch is good :)

> Sorry for not getting to them, but it's good they are
> merged.

cheers

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[kajoljain]

On 10/19/20 9:50 PM, Ian Rogers wrote:
> On Mon, Oct 19, 2020 at 2:51 AM John Garry <john.garry@huawei.com> wrote:
>>
>> On 19/10/2020 00:30, Ian Rogers wrote:
>>> On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
>>>>
>>>> Greeting,
>>>>
>>>> FYI, we noticed the following commit (built with gcc-9):
>>>>
>>>> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when covering multiple PMUs")
>>>> url: https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049
>>>>
>>>>
>>>> in testcase: perf-sanity-tests
>>>> version: perf-x86_64-c85fb28b6f99-1_20201008
>>>> with following parameters:
>>>>
>>>>          perf_compiler: gcc
>>>>          ucode: 0xdc
>>>>
>>>>
>>>>
>>>> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
>>>>
>>>> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):
>>>
>>> I believe this is a Skylake and there is a known bug in the Skylake
>>> metric DRAM_Parallel_Reads as described here:
>>> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
>>> Fixing the bug needs more knowledge than what is available in manuals.
>>> Hopefully Intel can take a look.
>>>
>>> Thanks,
>>> Ian
>>
>> So this named patch ("perf metricgroup: Hack a fix for aliases...") is
>> breaking test #67 on my machine also, which is a broadwell.
> 
> Thanks for taking a look John. If you want help you can send the
> output of "perf test 67 -vvv" to me. It is possible Broadwell has
> similar glitches in the json to Skylake. I tested the original test on
> server parts as I can access them as cloud machines.
> 
>> I will have a look, but I was hoping that Ian would have a proper fix
>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
>> which now looks to be merged.
> 
> I still have these changes to look at in my inbox but I'm assuming
> they're good :-) Sorry for not getting to them, but it's good they are
> merged.

Hi Ian,
   Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing. 
But I am getting issue in test 10 for powerpc

[command]# ./perf test 10 
10: PMU events                                                      :
10.1: PMU event table sanity                                        : Ok
10.2: PMU event map aliases                                         : Ok
10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!

Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.

So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
in function `metric_parse_fake`. I believe we need to send same value.
I will send fix patch for the same.

Thanks,
Kajol Jain

> 
> Thanks,
> Ian
> 
>> Thanks!
>>
>>>
>>>>
>>>>
>>>> If you fix the issue, kindly add following tag
>>>> Reported-by: kernel test robot <rong.a.chen@intel.com>
>>>>
>>>>
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 67
>>>> 67: Parse and process metrics                             : FAILED!
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 68
>>>> 68: x86 rdpmc                                             : Ok
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 69
>>>> 69: Convert perf time to TSC                              : Ok
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 70
>>>> 70: DWARF unwind                                          : Ok
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 71
>>>> 71: x86 instruction decoder - new instructions            : Ok
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 72
>>>> 72: Intel PT packet decoder                               : Ok
>>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 73
>>>> 73: x86 bp modify                                         : Ok
>>>> 2020-10-16 19:31:53 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 74
>>>> 74: probe libc's inet_pton & backtrace it with ping       : Ok
>>>> 2020-10-16 19:31:54 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 75
>>>> 75: Zstd perf.data compression/decompression              : Ok
>>>>
>>>>
>>>>
>>>> To reproduce:
>>>>
>>>>          git clone https://github.com/intel/lkp-tests.git
>>>>          cd lkp-tests
>>>>          bin/lkp install job.yaml  # job file is attached in this email
>>>>          bin/lkp run     job.yaml
>>>>
>>>>
>>>>
>>>> Thanks,
>>>> Rong Chen
>>>>
>>> .
>>>
>>

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Ian Rogers]

On Tue, Oct 20, 2020 at 1:56 AM kajoljain <kjain@linux.ibm.com> wrote:
>
>
>
> On 10/19/20 9:50 PM, Ian Rogers wrote:
> > On Mon, Oct 19, 2020 at 2:51 AM John Garry <john.garry@huawei.com> wrote:
> >>
> >> On 19/10/2020 00:30, Ian Rogers wrote:
> >>> On Sun, Oct 18, 2020 at 1:51 AM kernel test robot <rong.a.chen@intel.com> wrote:
> >>>>
> >>>> Greeting,
> >>>>
> >>>> FYI, we noticed the following commit (built with gcc-9):
> >>>>
> >>>> commit: fcc9c5243c478f104014daf4d23db86098d2aef0 ("perf metricgroup: Hack a fix for aliases when covering multiple PMUs")
> >>>> url: https://github.com/0day-ci/linux/commits/John-Garry/perf-pmu-events-Support-event-aliasing-for-system-PMUs/20201008-182049
> >>>>
> >>>>
> >>>> in testcase: perf-sanity-tests
> >>>> version: perf-x86_64-c85fb28b6f99-1_20201008
> >>>> with following parameters:
> >>>>
> >>>>          perf_compiler: gcc
> >>>>          ucode: 0xdc
> >>>>
> >>>>
> >>>>
> >>>> on test machine: 4 threads Intel(R) Core(TM) i5-6500 CPU @ 3.20GHz with 32G memory
> >>>>
> >>>> caused below changes (please refer to attached dmesg/kmsg for entire log/backtrace):
> >>>
> >>> I believe this is a Skylake and there is a known bug in the Skylake
> >>> metric DRAM_Parallel_Reads as described here:
> >>> https://lore.kernel.org/lkml/CAP-5=fXejVaQa9qfW66cY77qB962+jbe8tT5bsLoOOcFmODnWQ@mail.gmail.com/
> >>> Fixing the bug needs more knowledge than what is available in manuals.
> >>> Hopefully Intel can take a look.
> >>>
> >>> Thanks,
> >>> Ian
> >>
> >> So this named patch ("perf metricgroup: Hack a fix for aliases...") is
> >> breaking test #67 on my machine also, which is a broadwell.
> >
> > Thanks for taking a look John. If you want help you can send the
> > output of "perf test 67 -vvv" to me. It is possible Broadwell has
> > similar glitches in the json to Skylake. I tested the original test on
> > server parts as I can access them as cloud machines.
> >
> >> I will have a look, but I was hoping that Ian would have a proper fix
> >> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
> >> which now looks to be merged.
> >
> > I still have these changes to look at in my inbox but I'm assuming
> > they're good :-) Sorry for not getting to them, but it's good they are
> > merged.
>
> Hi Ian,
>    Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing.
> But I am getting issue in test 10 for powerpc
>
> [command]# ./perf test 10
> 10: PMU events                                                      :
> 10.1: PMU event table sanity                                        : Ok
> 10.2: PMU event map aliases                                         : Ok
> 10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
> 10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!
>
> Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.
>
> So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
> in function `metric_parse_fake`. I believe we need to send same value.
> I will send fix patch for the same.
>
> Thanks,
> Kajol Jain

Thanks, the fake support was done by Jiri. I do try to test on Power
8. The awesome thing, aside from the testing nit fixes, is that the
metrics will actually work once the test is passing :-). They may of
course report junk.

Thanks,
Ian

> >
> > Thanks,
> > Ian
> >
> >> Thanks!
> >>
> >>>
> >>>>
> >>>>
> >>>> If you fix the issue, kindly add following tag
> >>>> Reported-by: kernel test robot <rong.a.chen@intel.com>
> >>>>
> >>>>
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 67
> >>>> 67: Parse and process metrics                             : FAILED!
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 68
> >>>> 68: x86 rdpmc                                             : Ok
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 69
> >>>> 69: Convert perf time to TSC                              : Ok
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 70
> >>>> 70: DWARF unwind                                          : Ok
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 71
> >>>> 71: x86 instruction decoder - new instructions            : Ok
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 72
> >>>> 72: Intel PT packet decoder                               : Ok
> >>>> 2020-10-16 19:31:52 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 73
> >>>> 73: x86 bp modify                                         : Ok
> >>>> 2020-10-16 19:31:53 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 74
> >>>> 74: probe libc's inet_pton & backtrace it with ping       : Ok
> >>>> 2020-10-16 19:31:54 sudo /usr/src/perf_selftests-x86_64-rhel-8.3-fcc9c5243c478f104014daf4d23db86098d2aef0/tools/perf/perf test 75
> >>>> 75: Zstd perf.data compression/decompression              : Ok
> >>>>
> >>>>
> >>>>
> >>>> To reproduce:
> >>>>
> >>>>          git clone https://github.com/intel/lkp-tests.git
> >>>>          cd lkp-tests
> >>>>          bin/lkp install job.yaml  # job file is attached in this email
> >>>>          bin/lkp run     job.yaml
> >>>>
> >>>>
> >>>>
> >>>> Thanks,
> >>>> Rong Chen
> >>>>
> >>> .
> >>>
> >>

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[John Garry]

On 20/10/2020 17:53, Ian Rogers wrote:
>>> Thanks for taking a look John. If you want help you can send the
>>> output of "perf test 67 -vvv" to me. It is possible Broadwell has
>>> similar glitches in the json to Skylake. I tested the original test on
>>> server parts as I can access them as cloud machines.
>>>
>>>> I will have a look, but I was hoping that Ian would have a proper fix
>>>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
>>>> which now looks to be merged.
>>> I still have these changes to look at in my inbox but I'm assuming
>>> they're good:-)  Sorry for not getting to them, but it's good they are
>>> merged.
>> Hi Ian,
>>     Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing.
>> But I am getting issue in test 10 for powerpc
>>
>> [command]# ./perf test 10
>> 10: PMU events                                                      :
>> 10.1: PMU event table sanity                                        : Ok
>> 10.2: PMU event map aliases                                         : Ok
>> 10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
>> 10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!
>>
>> Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.
>>
>> So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
>> in function `metric_parse_fake`. I believe we need to send same value.
>> I will send fix patch for the same.

Just wondering, was a patch ever submitted for this? Something still 
broken? I can't see any recent relevant changes to tests/pmu-events.c

Thanks,
John

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[Ian Rogers]

On Tue, Nov 3, 2020 at 6:43 AM John Garry <john.garry@huawei.com> wrote:
>
> On 20/10/2020 17:53, Ian Rogers wrote:
> >>> Thanks for taking a look John. If you want help you can send the
> >>> output of "perf test 67 -vvv" to me. It is possible Broadwell has
> >>> similar glitches in the json to Skylake. I tested the original test on
> >>> server parts as I can access them as cloud machines.
> >>>
> >>>> I will have a look, but I was hoping that Ian would have a proper fix
> >>>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
> >>>> which now looks to be merged.
> >>> I still have these changes to look at in my inbox but I'm assuming
> >>> they're good:-)  Sorry for not getting to them, but it's good they are
> >>> merged.
> >> Hi Ian,
> >>     Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing.
> >> But I am getting issue in test 10 for powerpc
> >>
> >> [command]# ./perf test 10
> >> 10: PMU events                                                      :
> >> 10.1: PMU event table sanity                                        : Ok
> >> 10.2: PMU event map aliases                                         : Ok
> >> 10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
> >> 10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!
> >>
> >> Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.
> >>
> >> So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
> >> in function `metric_parse_fake`. I believe we need to send same value.
> >> I will send fix patch for the same.
>
> Just wondering, was a patch ever submitted for this? Something still
> broken? I can't see any recent relevant changes to tests/pmu-events.c

The test itself shouldn't have changed, but the json files parsed by
jevents and turned into C code that the test exercises should have
changed. Jin Yao has sent two patch sets fixing a metric issue on SKL
(Skylake non-server) that should hopefully fix the issue there - I'll
check the status on these. Are you testing on Skylake?

Thanks,
Ian

> Thanks,
> John

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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[John Garry]

On 03/11/2020 16:05, Ian Rogers wrote:
> On Tue, Nov 3, 2020 at 6:43 AM John Garry<john.garry@huawei.com>  wrote:
>> On 20/10/2020 17:53, Ian Rogers wrote:
>>>>> Thanks for taking a look John. If you want help you can send the
>>>>> output of "perf test 67 -vvv" to me. It is possible Broadwell has
>>>>> similar glitches in the json to Skylake. I tested the original test on
>>>>> server parts as I can access them as cloud machines.
>>>>>
>>>>>> I will have a look, but I was hoping that Ian would have a proper fix
>>>>>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
>>>>>> which now looks to be merged.
>>>>> I still have these changes to look at in my inbox but I'm assuming
>>>>> they're good:-)  Sorry for not getting to them, but it's good they are
>>>>> merged.
>>>> Hi Ian,
>>>>      Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing.
>>>> But I am getting issue in test 10 for powerpc
>>>>
>>>> [command]# ./perf test 10
>>>> 10: PMU events                                                      :
>>>> 10.1: PMU event table sanity                                        : Ok
>>>> 10.2: PMU event map aliases                                         : Ok
>>>> 10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
>>>> 10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!
>>>>
>>>> Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.
>>>>
>>>> So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
>>>> in function `metric_parse_fake`. I believe we need to send same value.
>>>> I will send fix patch for the same.
>> Just wondering, was a patch ever submitted for this? Something still
>> broken? I can't see any recent relevant changes to tests/pmu-events.c
> The test itself shouldn't have changed, but the json files parsed by
> jevents and turned into C code that the test exercises should have
> changed. Jin Yao has sent two patch sets fixing a metric issue on SKL
> (Skylake non-server) that should hopefully fix the issue there - I'll
> check the status on these. Are you testing on Skylake?

So I have re-read this thread, and it seems that 2x different things are 
being discussed:
a. some breakage for test #10 on skylake
b. test #67 being broken

It seems that a. has been addressed. That's what I was asking about just 
now.

So about b., which I thought may be broken for some other reason apart 
from my hacky patch. But it seems not the case, and a proper patch is 
needed there.

Ian, have you had a chance to consider this issue in b.? That is, we 
have breakage for metrics using uncore alias expressions for when 
multiple uncore PMUs associated exist in the system? As before, looks 
broken by ded80bda8bc9 ("perf expr: Migrate expr ids table to a hashmap")

Thanks,
John



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Re: [perf metricgroup] fcc9c5243c: perf-sanity-tests.Parse_and_process_metrics.fail

[kajoljain]

On 11/3/20 10:24 PM, John Garry wrote:
> On 03/11/2020 16:05, Ian Rogers wrote:
>> On Tue, Nov 3, 2020 at 6:43 AM John Garry<john.garry@huawei.com>  wrote:
>>> On 20/10/2020 17:53, Ian Rogers wrote:
>>>>>> Thanks for taking a look John. If you want help you can send the
>>>>>> output of "perf test 67 -vvv" to me. It is possible Broadwell has
>>>>>> similar glitches in the json to Skylake. I tested the original test on
>>>>>> server parts as I can access them as cloud machines.
>>>>>>
>>>>>>> I will have a look, but I was hoping that Ian would have a proper fix
>>>>>>> for this on top of ("perf metricgroup: Fix uncore metric expressions"),
>>>>>>> which now looks to be merged.
>>>>>> I still have these changes to look at in my inbox but I'm assuming
>>>>>> they're good:-)  Sorry for not getting to them, but it's good they are
>>>>>> merged.
>>>>> Hi Ian,
>>>>>      Checked in upstream kernel with your fix patch, in powerpc also test case 67 is passing.
>>>>> But I am getting issue in test 10 for powerpc
>>>>>
>>>>> [command]# ./perf test 10
>>>>> 10: PMU events                                                      :
>>>>> 10.1: PMU event table sanity                                        : Ok
>>>>> 10.2: PMU event map aliases                                         : Ok
>>>>> 10.3: Parsing of PMU event table metrics                            : Skip (some metrics failed)
>>>>> 10.4: Parsing of PMU event table metrics with fake PMUs             : FAILED!
>>>>>
>>>>> Was debugging it, issue is with commit e1c92a7fbbc5 perf tests: Add another metric parsing test.
>>>>>
>>>>> So, there we are passing different runtime parameter value in "expr__find_other and expr__parse"
>>>>> in function `metric_parse_fake`. I believe we need to send same value.
>>>>> I will send fix patch for the same.
>>> Just wondering, was a patch ever submitted for this? Something still
>>> broken? I can't see any recent relevant changes to tests/pmu-events.c
>> The test itself shouldn't have changed, but the json files parsed by
>> jevents and turned into C code that the test exercises should have
>> changed. Jin Yao has sent two patch sets fixing a metric issue on SKL
>> (Skylake non-server) that should hopefully fix the issue there - I'll
>> check the status on these. Are you testing on Skylake?
> 
> So I have re-read this thread, and it seems that 2x different things are being discussed:
> a. some breakage for test #10 on skylake
> b. test #67 being broken
> 
> It seems that a. has been addressed. That's what I was asking about just now.

Hi Ian/John,
        The breakage for test #10 which I mentioned is for power9 machine, if that you were asking.
I still need to send fix patch out. I will send it soon.

Thanks,
Kajol Jain

> 
> So about b., which I thought may be broken for some other reason apart from my hacky patch. But it seems not the case, and a proper patch is needed there.
> 
> Ian, have you had a chance to consider this issue in b.? That is, we have breakage for metrics using uncore alias expressions for when multiple uncore PMUs associated exist in the system? As before, looks broken by ded80bda8bc9 ("perf expr: Migrate expr ids table to a hashmap")
> 
> Thanks,
> John
> 
> 

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