From: Stephen Boyd <sboyd@kernel.org>
To: Andrew Jeffery <andrew@aj.id.au>, Joel Stanley <joel@jms.id.au>,
Michael Turquette <mturquette@baylibre.com>,
Ryan Chen <ryan_chen@aspeedtech.com>,
bmc-sw@aspeedtech.com, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Ryan Chen <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
Date: Tue, 13 Oct 2020 19:50:22 -0700 [thread overview]
Message-ID: <160264382296.310579.9835482254268204873@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20200928070108.14040-2-ryan_chen@aspeedtech.com>
Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side access SuperIO and SPI slave device.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
Is there resolution on this thread?
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next prev parent reply other threads:[~2020-10-14 2:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 7:01 [PATCH 0/1] Modify ASPEED SoC some default clks are critical Ryan Chen
2020-09-28 7:01 ` [PATCH 1/1] clk: aspeed: modify " Ryan Chen
2020-09-29 8:04 ` Joel Stanley
2020-09-29 8:37 ` Ryan Chen
2020-10-07 11:34 ` Joel Stanley
2020-10-08 2:33 ` Ryan Chen
2020-10-14 2:50 ` Stephen Boyd [this message]
2020-10-14 5:28 ` Joel Stanley
2020-10-14 5:39 ` Ryan Chen
2020-10-14 17:16 ` Stephen Boyd
2020-10-28 4:38 ` Joel Stanley
2020-10-29 2:25 ` Samuel Holland
2021-01-22 8:15 ` Ryan Chen
2021-01-25 0:47 ` Andrew Jeffery
2021-02-01 7:16 ` Ryan Chen
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