From: Stephen Boyd <sboyd@kernel.org>
To: Michael Tretter <m.tretter@pengutronix.de>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, m.mtretter@pengutronix.de,
michals@xilinx.com, kernel@pengutronix.de
Subject: Re: [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable
Date: Mon, 08 Feb 2021 18:35:20 -0800 [thread overview]
Message-ID: <161283812051.76967.2989359787806520148@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210121071659.1226489-11-m.tretter@pengutronix.de>
Quoting Michael Tretter (2021-01-20 23:16:54)
> Do not configure the PLL when probing the driver, but register the clock
> in the clock framework and do the configuration based on the respective
> callbacks.
>
> This is necessary to allow the consumers, i.e., encoder and decoder
> drivers, of the xlnx_vcu clock provider to set the clock rate and
> actually enable the clocks without relying on some pre-configuration.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> ---
Applied to clk-next
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next prev parent reply other threads:[~2021-02-09 2:37 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 7:16 [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter
2021-01-21 7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter
2021-02-09 2:32 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter
2021-02-09 2:35 ` Stephen Boyd [this message]
2021-01-21 7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
2021-01-21 7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter
2021-02-09 2:35 ` Stephen Boyd
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