From: Flora Fu <flora.fu@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>
Cc: Flora Fu <flora.fu@mediatek.com>,
Pi-Cheng Chen <pi-cheng.chen@mediatek.com>,
Chiawen Lee <chiawen.lee@mediatek.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>
Subject: [PATCH 5/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
Date: Wed, 7 Apr 2021 11:28:03 +0800 [thread overview]
Message-ID: <1617766086-5502-6-git-send-email-flora.fu@mediatek.com> (raw)
In-Reply-To: <1617766086-5502-1-git-send-email-flora.fu@mediatek.com>
Document the bindings for APU power domain on MediaTek SoC.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
---
.../soc/mediatek/mediatek,apu-pm.yaml | 146 ++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
new file mode 100644
index 000000000000..c99e812977f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek APU Power Domains
+
+maintainers:
+ - Flora Fu <flora.fu@mediatek.com>
+
+description: |
+ Mediatek AI Process Unit (APU) include support for power domains which can be
+ powered up/down by software.
+ APU subsys belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for apuspm node representing the domain.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8192-apu-pm
+ - const: syscon
+
+ reg:
+ description: Address range of the APU power domain controller.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#power-domain-cells':
+ const: 1
+
+ vsram-supply:
+ description: apu sram regulator supply.
+
+ mediatek,scpsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys register range.
+
+ mediatek,apu_conn:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu conn register range.
+
+ mediatek,apu_conn1:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu conn1 register range.
+
+ mediatek,apu_vcore:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu vcore register range.
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents the power domains within the power controller node as
+ documented in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ properties:
+ reg:
+ description: |
+ Power domain index. Valid values are defined in:
+ "include/dt-bindings/power/mt8182-apu-power.h"
+ maxItems: 1
+
+ '#power-domain-cells':
+ description: |
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM.
+
+ clocks:
+ description: |
+ List of phandles of clocks list. Specify by order according to
+ power-up sequence.
+
+ clock-names:
+ description: |
+ List of names of clocks. Specify by order according to power-up
+ sequence.
+
+ assigned-clocks:
+ maxItems: 2
+
+ assigned-clock-parents:
+ maxItems: 2
+
+ domain-supply:
+ description: domain regulator supply.
+
+ required:
+ - reg
+ - '#power-domain-cells'
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - vsram-supply
+ - mediatek,scpsys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/power/mt8192-apu-power.h>
+ apuspm: power-domain@190f0000 {
+ compatible = "mediatek,mt8192-apu-pm", "syscon";
+ reg = <0x190f0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ vsram-supply = <&mt6359_vsram_md_ldo_reg>;
+ mediatek,scpsys = <&scpsys>;
+ mediatek,apu_conn = <&apu_conn>;
+ mediatek,apu_vcore = <&apu_vcore>;
+
+ power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+ reg = <MT8192_POWER_DOMAIN_APUSYS_TOP>;
+ #power-domain-cells = <0>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+ assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ domain-supply = <&mt6359_vproc1_buck_reg>;
+ };
+ };
--
2.18.0
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next prev parent reply other threads:[~2021-04-07 3:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 3:27 [PATCH 0/8] Add Support for MediaTek MT8192 APU Power Flora Fu
2021-04-07 3:27 ` [PATCH 1/8] dt-bindings: clock: Add MT8192 APU clock bindings Flora Fu
2021-04-09 18:09 ` Rob Herring
2021-04-07 3:28 ` [PATCH 2/8] clk: mediatek: mt8192: Add APU clocks support Flora Fu
2021-04-07 3:28 ` [PATCH 3/8] dt-bindings: apu: Add MT8192 APU power domain Flora Fu
2021-04-09 18:23 ` Rob Herring
2021-04-12 7:19 ` Flora Fu
2021-04-07 3:28 ` [PATCH 4/8] dt-bindings: arm: mediatek: Add new document bindings for APU Flora Fu
2021-04-09 18:25 ` Rob Herring
2021-04-12 6:44 ` Flora Fu
2021-04-15 21:24 ` Rob Herring
2021-04-16 3:01 ` Flora Fu
2021-04-07 3:28 ` Flora Fu [this message]
2021-04-07 14:28 ` [PATCH 5/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain Rob Herring
2021-04-08 4:03 ` Flora Fu
2021-04-07 3:28 ` [PATCH 6/8] soc: mediatek: apu: Add apusys and add apu power domain driver Flora Fu
2021-04-07 3:28 ` [PATCH 7/8] arm64: dts: mt8192: Add APU node Flora Fu
2021-04-07 3:28 ` [PATCH 8/8] arm64: dts: mt8192: Add APU power domain node Flora Fu
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