From: Catalin Marinas <catalin.marinas@arm.com>
To: linux-arm-kernel@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>, maz@kernel.org, yuzenghui@huawei.com
Subject: Re: [PATCH] arm64: entry: always set GIC_PRIO_PSR_I_SET during entry
Date: Wed, 5 May 2021 18:42:57 +0100 [thread overview]
Message-ID: <162023655036.12774.16723869414268323930.b4-ty@arm.com> (raw)
In-Reply-To: <20210428111555.50880-1-mark.rutland@arm.com>
On Wed, 28 Apr 2021 12:15:55 +0100, Mark Rutland wrote:
> Zenghui reports that booting a kernel with "irqchip.gicv3_pseudo_nmi=1"
> on the command line hits a warning during kernel entry, due to the way
> we manipulate the PMR.
>
> Early in the entry sequence, we call lockdep_hardirqs_off() to inform
> lockdep that interrupts have been masked (as the HW sets DAIF wqhen
> entering an exception). Architecturally PMR_EL1 is not affected by
> exception entry, and we don't set GIC_PRIO_PSR_I_SET in the PMR early in
> the exception entry sequence, so early in exception entry the PMR can
> indicate that interrupts are unmasked even though they are masked by
> DAIF.
>
> [...]
Applied to arm64 (for-next/core), thanks!
[1/1] arm64: entry: always set GIC_PRIO_PSR_I_SET during entry
https://git.kernel.org/arm64/c/4d6a38da8e79
--
Catalin
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prev parent reply other threads:[~2021-05-05 17:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 11:15 [PATCH] arm64: entry: always set GIC_PRIO_PSR_I_SET during entry Mark Rutland
2021-04-28 14:41 ` Marc Zyngier
2021-04-28 15:19 ` Mark Rutland
2021-04-28 15:29 ` Mark Rutland
2021-05-05 14:41 ` Marc Zyngier
2021-05-05 17:42 ` Catalin Marinas [this message]
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