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* [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits
@ 2021-05-19 17:41 Peter Geis
  2021-05-20  1:26 ` elaine.zhang
  2021-05-23 23:51 ` Heiko Stuebner
  0 siblings, 2 replies; 3+ messages in thread
From: Peter Geis @ 2021-05-19 17:41 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Heiko Stuebner, Kever Yang,
	Elaine Zhang
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel, Peter Geis

The cpll clk gate bits had an ordering issue. This led to the loss of
the boot sdmmc controller when the gmac was shut down with:
`ip link set eth0 down`
as the cpll_100m was shut off instead of the cpll_62p5.
cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
misplaced.

Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568")

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/clk/rockchip/clk-rk3568.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 946ea2f45bf3..75ca855e720d 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
 			RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
 			RK3568_CLKGATE_CON(35), 10, GFLAGS),
+	COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
+			RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
+			RK3568_CLKGATE_CON(35), 11, GFLAGS),
 	COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
 			RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
-			RK3568_CLKGATE_CON(35), 11, GFLAGS),
+			RK3568_CLKGATE_CON(35), 12, GFLAGS),
 	COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
 			RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
-			RK3568_CLKGATE_CON(35), 12, GFLAGS),
+			RK3568_CLKGATE_CON(35), 13, GFLAGS),
 	COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
 			RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
-			RK3568_CLKGATE_CON(35), 13, GFLAGS),
-	COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
-			RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
 			RK3568_CLKGATE_CON(35), 14, GFLAGS),
 	COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
 			RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits
  2021-05-19 17:41 [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits Peter Geis
@ 2021-05-20  1:26 ` elaine.zhang
  2021-05-23 23:51 ` Heiko Stuebner
  1 sibling, 0 replies; 3+ messages in thread
From: elaine.zhang @ 2021-05-20  1:26 UTC (permalink / raw)
  To: Peter Geis, Michael Turquette, Stephen Boyd, Heiko Stuebner, Kever Yang
  Cc: linux-clk, linux-arm-kernel, linux-rockchip, linux-kernel

Hi: Michael:

Thanks for your patch.

Reviewed-by: Elaine Zhang<zhangqing@rock-chips.com>

在 2021/5/20 上午1:41, Peter Geis 写道:
> The cpll clk gate bits had an ordering issue. This led to the loss of
> the boot sdmmc controller when the gmac was shut down with:
> `ip link set eth0 down`
> as the cpll_100m was shut off instead of the cpll_62p5.
> cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
> misplaced.
>
> Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568")
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>   drivers/clk/rockchip/clk-rk3568.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index 946ea2f45bf3..75ca855e720d 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
>   	COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
>   			RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
>   			RK3568_CLKGATE_CON(35), 10, GFLAGS),
> +	COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
> +			RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
> +			RK3568_CLKGATE_CON(35), 11, GFLAGS),
>   	COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
>   			RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
> -			RK3568_CLKGATE_CON(35), 11, GFLAGS),
> +			RK3568_CLKGATE_CON(35), 12, GFLAGS),
>   	COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
>   			RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
> -			RK3568_CLKGATE_CON(35), 12, GFLAGS),
> +			RK3568_CLKGATE_CON(35), 13, GFLAGS),
>   	COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
>   			RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
> -			RK3568_CLKGATE_CON(35), 13, GFLAGS),
> -	COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
> -			RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
>   			RK3568_CLKGATE_CON(35), 14, GFLAGS),
>   	COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
>   			RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,



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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits
  2021-05-19 17:41 [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits Peter Geis
  2021-05-20  1:26 ` elaine.zhang
@ 2021-05-23 23:51 ` Heiko Stuebner
  1 sibling, 0 replies; 3+ messages in thread
From: Heiko Stuebner @ 2021-05-23 23:51 UTC (permalink / raw)
  To: Kever Yang, Elaine Zhang, Peter Geis, Stephen Boyd, Michael Turquette
  Cc: Heiko Stuebner, linux-rockchip, linux-arm-kernel, linux-kernel,
	linux-clk

On Wed, 19 May 2021 13:41:49 -0400, Peter Geis wrote:
> The cpll clk gate bits had an ordering issue. This led to the loss of
> the boot sdmmc controller when the gmac was shut down with:
> `ip link set eth0 down`
> as the cpll_100m was shut off instead of the cpll_62p5.
> cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
> misplaced.
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: fix rk3568 cpll clk gate bits
      commit: 2f3877d609e7951ef96d24979eb9d163f1f004f8

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-05-24 17:00 UTC | newest]

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2021-05-19 17:41 [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits Peter Geis
2021-05-20  1:26 ` elaine.zhang
2021-05-23 23:51 ` Heiko Stuebner

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