* [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS
@ 2021-05-11 18:23 Catalin Marinas
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Catalin Marinas @ 2021-05-11 18:23 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
Hi,
The GMID_EL1.BS field determines the number of tags accessed by
STGM/LDGM. While I haven't heard of a system where this field differs
across CPUs in a system, it's better to check.
In addition, "upgrade" the sysreg storage in struct cpuinfo_arm64 to
u64.
Catalin Marinas (2):
arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
arm64: Check if GMID_EL1.BS is the same on all CPUs
arch/arm64/include/asm/cpu.h | 11 ++++++-----
arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++
arch/arm64/kernel/cpuinfo.c | 3 ++-
3 files changed, 25 insertions(+), 6 deletions(-)
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-11 18:23 [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
@ 2021-05-11 18:23 ` Catalin Marinas
2021-05-12 13:29 ` Mark Rutland
` (2 more replies)
2021-05-11 18:23 ` [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
2021-05-25 18:58 ` [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Will Deacon
2 siblings, 3 replies; 13+ messages in thread
From: Catalin Marinas @ 2021-05-11 18:23 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
The architecture has been updated and the CTR_EL0, CNTFRQ_EL1,
DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most
of them have a RES0 top 32-bit.
Change their type to u64 in struct cpuinfo_arm64.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
---
CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have
no idea what software is supposed to do with this field. I even have a
Jira ticket from 2019 asking for it to be removed. So I don't think we
should bother adding the mask/checks for it to the kernel.
arch/arm64/include/asm/cpu.h | 10 +++++-----
arch/arm64/kernel/cpuinfo.c | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index 7faae6ff3ab4..fe5a8499ddc2 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -15,11 +15,11 @@
struct cpuinfo_arm64 {
struct cpu cpu;
struct kobject kobj;
- u32 reg_ctr;
- u32 reg_cntfrq;
- u32 reg_dczid;
- u32 reg_midr;
- u32 reg_revidr;
+ u64 reg_ctr;
+ u64 reg_cntfrq;
+ u64 reg_dczid;
+ u64 reg_midr;
+ u64 reg_revidr;
u64 reg_id_aa64dfr0;
u64 reg_id_aa64dfr1;
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 77605aec25fe..4bea701117d4 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = {
struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
\
if (info->reg_midr) \
- return sprintf(buf, "0x%016x\n", info->reg_##_field); \
+ return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
else \
return 0; \
} \
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-11 18:23 [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
@ 2021-05-11 18:23 ` Catalin Marinas
2021-05-12 13:33 ` Mark Rutland
2021-05-26 19:47 ` Jon Hunter
2021-05-25 18:58 ` [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Will Deacon
2 siblings, 2 replies; 13+ messages in thread
From: Catalin Marinas @ 2021-05-11 18:23 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
The GMID_EL1.BS field determines the number of tags accessed by the
LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
zeroing page tags.
Taint the kernel if GMID_EL1.BS differs between CPUs.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
---
arch/arm64/include/asm/cpu.h | 1 +
arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++
arch/arm64/kernel/cpuinfo.c | 1 +
3 files changed, 19 insertions(+)
diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index fe5a8499ddc2..9088e72c7cf6 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -20,6 +20,7 @@ struct cpuinfo_arm64 {
u64 reg_dczid;
u64 reg_midr;
u64 reg_revidr;
+ u64 reg_gmid;
u64 reg_id_aa64dfr0;
u64 reg_id_aa64dfr1;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index ca66a61bb396..3b9089ca52dc 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -401,6 +401,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_gmid[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_id_isar0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
@@ -618,6 +623,9 @@ static const struct __ftr_reg_entry {
/* Op1 = 0, CRn = 1, CRm = 2 */
ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
+ /* Op1 = 1, CRn = 0, CRm = 0 */
+ ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
+
/* Op1 = 3, CRn = 0, CRm = 0 */
{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
@@ -872,6 +880,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
+ init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
@@ -1082,6 +1091,14 @@ void update_cpu_features(int cpu,
taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
info->reg_dczid, boot->reg_dczid);
+ /*
+ * The kernel uses the LDGM/STGM instructions and the number of tags
+ * they read/write depends on the GMID_EL1.BS field. Check that the
+ * value is the same on all CPUs.
+ */
+ taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
+ info->reg_gmid, boot->reg_gmid);
+
/* If different, timekeeping will be broken (especially with KVM) */
taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
info->reg_cntfrq, boot->reg_cntfrq);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 4bea701117d4..cd9f2d51285b 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -359,6 +359,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
info->reg_dczid = read_cpuid(DCZID_EL0);
info->reg_midr = read_cpuid_id();
info->reg_revidr = read_cpuid(REVIDR_EL1);
+ info->reg_gmid = read_cpuid(GMID_EL1);
info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
@ 2021-05-12 13:29 ` Mark Rutland
2021-05-12 13:54 ` Suzuki K Poulose
2021-05-24 1:31 ` Shaokun Zhang
2 siblings, 0 replies; 13+ messages in thread
From: Mark Rutland @ 2021-05-12 13:29 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-arm-kernel, Will Deacon, Suzuki K Poulose
On Tue, May 11, 2021 at 07:23:21PM +0100, Catalin Marinas wrote:
> The architecture has been updated and the CTR_EL0, CNTFRQ_EL1,
> DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most
> of them have a RES0 top 32-bit.
>
> Change their type to u64 in struct cpuinfo_arm64.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
>
> CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have
> no idea what software is supposed to do with this field. I even have a
> Jira ticket from 2019 asking for it to be removed. So I don't think we
> should bother adding the mask/checks for it to the kernel.
>
> arch/arm64/include/asm/cpu.h | 10 +++++-----
> arch/arm64/kernel/cpuinfo.c | 2 +-
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 7faae6ff3ab4..fe5a8499ddc2 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -15,11 +15,11 @@
> struct cpuinfo_arm64 {
> struct cpu cpu;
> struct kobject kobj;
> - u32 reg_ctr;
> - u32 reg_cntfrq;
> - u32 reg_dczid;
> - u32 reg_midr;
> - u32 reg_revidr;
> + u64 reg_ctr;
> + u64 reg_cntfrq;
> + u64 reg_dczid;
> + u64 reg_midr;
> + u64 reg_revidr;
>
> u64 reg_id_aa64dfr0;
> u64 reg_id_aa64dfr1;
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 77605aec25fe..4bea701117d4 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = {
> struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
> \
> if (info->reg_midr) \
> - return sprintf(buf, "0x%016x\n", info->reg_##_field); \
> + return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
> else \
> return 0; \
> } \
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-11 18:23 ` [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
@ 2021-05-12 13:33 ` Mark Rutland
2021-05-26 19:47 ` Jon Hunter
1 sibling, 0 replies; 13+ messages in thread
From: Mark Rutland @ 2021-05-12 13:33 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-arm-kernel, Will Deacon, Suzuki K Poulose
On Tue, May 11, 2021 at 07:23:22PM +0100, Catalin Marinas wrote:
> The GMID_EL1.BS field determines the number of tags accessed by the
> LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
> zeroing page tags.
>
> Taint the kernel if GMID_EL1.BS differs between CPUs.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
> arch/arm64/include/asm/cpu.h | 1 +
> arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++
> arch/arm64/kernel/cpuinfo.c | 1 +
> 3 files changed, 19 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index fe5a8499ddc2..9088e72c7cf6 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -20,6 +20,7 @@ struct cpuinfo_arm64 {
> u64 reg_dczid;
> u64 reg_midr;
> u64 reg_revidr;
> + u64 reg_gmid;
>
> u64 reg_id_aa64dfr0;
> u64 reg_id_aa64dfr1;
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index ca66a61bb396..3b9089ca52dc 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -401,6 +401,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
> ARM64_FTR_END,
> };
>
> +static const struct arm64_ftr_bits ftr_gmid[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
> +
> static const struct arm64_ftr_bits ftr_id_isar0[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
> @@ -618,6 +623,9 @@ static const struct __ftr_reg_entry {
> /* Op1 = 0, CRn = 1, CRm = 2 */
> ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
>
> + /* Op1 = 1, CRn = 0, CRm = 0 */
> + ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
> +
> /* Op1 = 3, CRn = 0, CRm = 0 */
> { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
> ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
> @@ -872,6 +880,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
> init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
> init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
> init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
> + init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
> init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
> init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
> init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
> @@ -1082,6 +1091,14 @@ void update_cpu_features(int cpu,
> taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
> info->reg_dczid, boot->reg_dczid);
>
> + /*
> + * The kernel uses the LDGM/STGM instructions and the number of tags
> + * they read/write depends on the GMID_EL1.BS field. Check that the
> + * value is the same on all CPUs.
> + */
> + taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
> + info->reg_gmid, boot->reg_gmid);
> +
> /* If different, timekeeping will be broken (especially with KVM) */
> taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
> info->reg_cntfrq, boot->reg_cntfrq);
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 4bea701117d4..cd9f2d51285b 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -359,6 +359,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
> info->reg_dczid = read_cpuid(DCZID_EL0);
> info->reg_midr = read_cpuid_id();
> info->reg_revidr = read_cpuid(REVIDR_EL1);
> + info->reg_gmid = read_cpuid(GMID_EL1);
>
> info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
> info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
2021-05-12 13:29 ` Mark Rutland
@ 2021-05-12 13:54 ` Suzuki K Poulose
2021-05-24 1:31 ` Shaokun Zhang
2 siblings, 0 replies; 13+ messages in thread
From: Suzuki K Poulose @ 2021-05-12 13:54 UTC (permalink / raw)
To: Catalin Marinas, linux-arm-kernel; +Cc: Will Deacon, Mark Rutland
On 11/05/2021 19:23, Catalin Marinas wrote:
> The architecture has been updated and the CTR_EL0, CNTFRQ_EL1,
> DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most
> of them have a RES0 top 32-bit.
>
> Change their type to u64 in struct cpuinfo_arm64.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
> ---
>
> CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have
> no idea what software is supposed to do with this field. I even have a
> Jira ticket from 2019 asking for it to be removed. So I don't think we
> should bother adding the mask/checks for it to the kernel.
>
> arch/arm64/include/asm/cpu.h | 10 +++++-----
> arch/arm64/kernel/cpuinfo.c | 2 +-
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
2021-05-12 13:29 ` Mark Rutland
2021-05-12 13:54 ` Suzuki K Poulose
@ 2021-05-24 1:31 ` Shaokun Zhang
2021-05-26 16:07 ` Catalin Marinas
2 siblings, 1 reply; 13+ messages in thread
From: Shaokun Zhang @ 2021-05-24 1:31 UTC (permalink / raw)
To: Catalin Marinas, linux-arm-kernel
Cc: Will Deacon, Mark Rutland, Suzuki K Poulose
Hi Catalin,
On 2021/5/12 2:23, Catalin Marinas wrote:
> The architecture has been updated and the CTR_EL0, CNTFRQ_EL1,
s/CNTFRQ_EL1/CNTFRQ_EL0?
> DCZID_EL0, MIDR_EL1, REVIDR_EL1 registers are all 64-bit, even if most
> of them have a RES0 top 32-bit.
>
> Change their type to u64 in struct cpuinfo_arm64.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
> ---
>
> CTR_EL0 gained a new field with MTE in the top 32-bit, TminLine. I have
> no idea what software is supposed to do with this field. I even have a
> Jira ticket from 2019 asking for it to be removed. So I don't think we
> should bother adding the mask/checks for it to the kernel.
>
> arch/arm64/include/asm/cpu.h | 10 +++++-----
> arch/arm64/kernel/cpuinfo.c | 2 +-
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 7faae6ff3ab4..fe5a8499ddc2 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -15,11 +15,11 @@
> struct cpuinfo_arm64 {
> struct cpu cpu;
> struct kobject kobj;
> - u32 reg_ctr;
> - u32 reg_cntfrq;
> - u32 reg_dczid;
> - u32 reg_midr;
> - u32 reg_revidr;
> + u64 reg_ctr;
> + u64 reg_cntfrq;
One more question: is it ok to change the function prototype to u64 also?
For CNTFRQ_EL0, if the Arm ARM expand the clock to more than 4GHz and it
will also work this change (arch_timer and watchdog shall change at the
the same time).
Thanks,
Shaokun
> + u64 reg_dczid;
> + u64 reg_midr;
> + u64 reg_revidr;
>
> u64 reg_id_aa64dfr0;
> u64 reg_id_aa64dfr1;
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 77605aec25fe..4bea701117d4 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -246,7 +246,7 @@ static struct kobj_type cpuregs_kobj_type = {
> struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
> \
> if (info->reg_midr) \
> - return sprintf(buf, "0x%016x\n", info->reg_##_field); \
> + return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
> else \
> return 0; \
> } \
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> .
>
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS
2021-05-11 18:23 [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
2021-05-11 18:23 ` [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
@ 2021-05-25 18:58 ` Will Deacon
2 siblings, 0 replies; 13+ messages in thread
From: Will Deacon @ 2021-05-25 18:58 UTC (permalink / raw)
To: linux-arm-kernel, Catalin Marinas
Cc: kernel-team, Will Deacon, Suzuki K Poulose, Mark Rutland
On Tue, 11 May 2021 19:23:20 +0100, Catalin Marinas wrote:
> The GMID_EL1.BS field determines the number of tags accessed by
> STGM/LDGM. While I haven't heard of a system where this field differs
> across CPUs in a system, it's better to check.
>
> In addition, "upgrade" the sysreg storage in struct cpuinfo_arm64 to
> u64.
>
> [...]
Applied to arm64 (for-next/cpufeature), thanks!
[1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
https://git.kernel.org/arm64/c/0f7b586f8fe7
[2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
https://git.kernel.org/arm64/c/71b7566d3fd6
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
2021-05-24 1:31 ` Shaokun Zhang
@ 2021-05-26 16:07 ` Catalin Marinas
0 siblings, 0 replies; 13+ messages in thread
From: Catalin Marinas @ 2021-05-26 16:07 UTC (permalink / raw)
To: Shaokun Zhang
Cc: linux-arm-kernel, Will Deacon, Mark Rutland, Suzuki K Poulose
On Mon, May 24, 2021 at 09:31:24AM +0800, Shaokun Zhang wrote:
> On 2021/5/12 2:23, Catalin Marinas wrote:
> > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> > index 7faae6ff3ab4..fe5a8499ddc2 100644
> > --- a/arch/arm64/include/asm/cpu.h
> > +++ b/arch/arm64/include/asm/cpu.h
> > @@ -15,11 +15,11 @@
> > struct cpuinfo_arm64 {
> > struct cpu cpu;
> > struct kobject kobj;
> > - u32 reg_ctr;
> > - u32 reg_cntfrq;
> > - u32 reg_dczid;
> > - u32 reg_midr;
> > - u32 reg_revidr;
> > + u64 reg_ctr;
> > + u64 reg_cntfrq;
>
> One more question: is it ok to change the function prototype to u64 also?
> For CNTFRQ_EL0, if the Arm ARM expand the clock to more than 4GHz and it
> will also work this change (arch_timer and watchdog shall change at the
> the same time).
I think I'll keep cntfrq as u32. It matches the function prototype and
the arm32 code which shares the same driver. Also, from ARMv8.6, there's
a requirement that CNTFRQ_EL0 is standardised at 1GHz.
--
Catalin
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-11 18:23 ` [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
2021-05-12 13:33 ` Mark Rutland
@ 2021-05-26 19:47 ` Jon Hunter
2021-05-26 21:08 ` Will Deacon
2021-05-26 21:48 ` Catalin Marinas
1 sibling, 2 replies; 13+ messages in thread
From: Jon Hunter @ 2021-05-26 19:47 UTC (permalink / raw)
To: Catalin Marinas, linux-arm-kernel
Cc: Will Deacon, Mark Rutland, Suzuki K Poulose, linux-tegra
On 11/05/2021 19:23, Catalin Marinas wrote:
> The GMID_EL1.BS field determines the number of tags accessed by the
> LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
> zeroing page tags.
>
> Taint the kernel if GMID_EL1.BS differs between CPUs.
>
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
> ---
> arch/arm64/include/asm/cpu.h | 1 +
> arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++
> arch/arm64/kernel/cpuinfo.c | 1 +
> 3 files changed, 19 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index fe5a8499ddc2..9088e72c7cf6 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -20,6 +20,7 @@ struct cpuinfo_arm64 {
> u64 reg_dczid;
> u64 reg_midr;
> u64 reg_revidr;
> + u64 reg_gmid;
>
> u64 reg_id_aa64dfr0;
> u64 reg_id_aa64dfr1;
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index ca66a61bb396..3b9089ca52dc 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -401,6 +401,11 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
> ARM64_FTR_END,
> };
>
> +static const struct arm64_ftr_bits ftr_gmid[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
> +
> static const struct arm64_ftr_bits ftr_id_isar0[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
> @@ -618,6 +623,9 @@ static const struct __ftr_reg_entry {
> /* Op1 = 0, CRn = 1, CRm = 2 */
> ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
>
> + /* Op1 = 1, CRn = 0, CRm = 0 */
> + ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
> +
> /* Op1 = 3, CRn = 0, CRm = 0 */
> { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
> ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
> @@ -872,6 +880,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
> init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
> init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
> init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
> + init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
> init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
> init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
> init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
> @@ -1082,6 +1091,14 @@ void update_cpu_features(int cpu,
> taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
> info->reg_dczid, boot->reg_dczid);
>
> + /*
> + * The kernel uses the LDGM/STGM instructions and the number of tags
> + * they read/write depends on the GMID_EL1.BS field. Check that the
> + * value is the same on all CPUs.
> + */
> + taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
> + info->reg_gmid, boot->reg_gmid);
> +
> /* If different, timekeeping will be broken (especially with KVM) */
> taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
> info->reg_cntfrq, boot->reg_cntfrq);
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 4bea701117d4..cd9f2d51285b 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -359,6 +359,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
> info->reg_dczid = read_cpuid(DCZID_EL0);
> info->reg_midr = read_cpuid_id();
> info->reg_revidr = read_cpuid(REVIDR_EL1);
> + info->reg_gmid = read_cpuid(GMID_EL1);
>
> info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
> info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
I am seeing the following undefined instruction crash on all our
ARM64 Tegra devices on today's -next and bisect is pointing to
this patch. Reverting this patch on top of -next does fix the
problem. Let me know if you have any thoughts.
Thanks!
Jon
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] kernel BUG at /dvs/git/dirty/git-master_l4t-upstream/kernel/arch/arm64/kernel/traps.c:406!
[ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.13.0-rc3-next-20210526-gf6b46ef27317 #1
[ 0.000000] Hardware name: NVIDIA Jetson TX2 Developer Kit (DT)
[ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO BTYPE=--)
[ 0.000000] pc : do_undefinstr+0x298/0x2b0
[ 0.000000] lr : do_undefinstr+0x2a8/0x2b0
[ 0.000000] sp : ffff800011cb3c10
[ 0.000000] x29: ffff800011cb3c10 x28: ffff800011cc3540 x27: 0000000000000002
[ 0.000000] x26: ffff800011760008 x25: ffff0001f4deccc0 x24: ffff800011cb9000
[ 0.000000] x23: ffff800011fb50f8 x22: ffff800011fb5000 x21: 00000000d5390080
[ 0.000000] x20: ffff800011cb3c90 x19: ffff800011cb9000 x18: ffffffffffffffff
[ 0.000000] x17: 0000000000017000 x16: 0000000000000000 x15: 000000000000001e
[ 0.000000] x14: 0000000000200000 x13: 0000000275e00000 x12: 0000001000000000
[ 0.000000] x11: 00000000009fc580 x10: 0000000274e03a80 x9 : 0000001000000000
[ 0.000000] x8 : 0000000000200000 x7 : 0000000000000003 x6 : 0000000000000000
[ 0.000000] x5 : ffff800011cc5910 x4 : 0000000000000000 x3 : ffff800011fb50f8
[ 0.000000] x2 : 0000000000000000 x1 : ffff800011cc3540 x0 : 0000000000000005
[ 0.000000] Call trace:
[ 0.000000] do_undefinstr+0x298/0x2b0
[ 0.000000] el1_undef+0x2c/0x48
[ 0.000000] el1_sync_handler+0xb4/0xd0
[ 0.000000] el1_sync+0x74/0x100
[ 0.000000] __cpuinfo_store_cpu+0x5c/0x248
[ 0.000000] cpuinfo_store_boot_cpu+0x28/0x54
[ 0.000000] smp_prepare_boot_cpu+0x2c/0x38
[ 0.000000] start_kernel+0x1a4/0x62c
[ 0.000000] __primary_switched+0x8c/0x90
[ 0.000000] Code: b5fffe40 b94047b5 17ffffca d503201f (d4210000)
[ 0.000000] random: get_random_bytes called from print_oops_end_marker+0x4c/0x68 with crng_init=0
[ 0.000000] ---[ end trace 0000000000000000 ]---
--
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-26 19:47 ` Jon Hunter
@ 2021-05-26 21:08 ` Will Deacon
2021-05-26 21:48 ` Catalin Marinas
1 sibling, 0 replies; 13+ messages in thread
From: Will Deacon @ 2021-05-26 21:08 UTC (permalink / raw)
To: Jon Hunter
Cc: Catalin Marinas, linux-arm-kernel, Mark Rutland,
Suzuki K Poulose, linux-tegra
On Wed, May 26, 2021 at 08:47:16PM +0100, Jon Hunter wrote:
> On 11/05/2021 19:23, Catalin Marinas wrote:
> > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> > index 4bea701117d4..cd9f2d51285b 100644
> > --- a/arch/arm64/kernel/cpuinfo.c
> > +++ b/arch/arm64/kernel/cpuinfo.c
> > @@ -359,6 +359,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
> > info->reg_dczid = read_cpuid(DCZID_EL0);
> > info->reg_midr = read_cpuid_id();
> > info->reg_revidr = read_cpuid(REVIDR_EL1);
> > + info->reg_gmid = read_cpuid(GMID_EL1);
> >
> > info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
> > info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
>
>
> I am seeing the following undefined instruction crash on all our
> ARM64 Tegra devices on today's -next and bisect is pointing to
> this patch. Reverting this patch on top of -next does fix the
> problem. Let me know if you have any thoughts.
Catalin just posted a fixed version, so should be solved asap (I'll push a
new branch shortly).
Thanks!
Will
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-26 19:47 ` Jon Hunter
2021-05-26 21:08 ` Will Deacon
@ 2021-05-26 21:48 ` Catalin Marinas
2021-05-26 22:11 ` Jon Hunter
1 sibling, 1 reply; 13+ messages in thread
From: Catalin Marinas @ 2021-05-26 21:48 UTC (permalink / raw)
To: Jon Hunter
Cc: linux-arm-kernel, Will Deacon, Mark Rutland, Suzuki K Poulose,
linux-tegra
On Wed, May 26, 2021 at 08:47:16PM +0100, Jon Hunter wrote:
> On 11/05/2021 19:23, Catalin Marinas wrote:
> > The GMID_EL1.BS field determines the number of tags accessed by the
> > LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
> > zeroing page tags.
> >
> > Taint the kernel if GMID_EL1.BS differs between CPUs.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
[...]
> I am seeing the following undefined instruction crash on all our
> ARM64 Tegra devices on today's -next and bisect is pointing to
> this patch. Reverting this patch on top of -next does fix the
> problem. Let me know if you have any thoughts.
Yeah, sorry about that. Posted a new version here, better tested:
https://lore.kernel.org/r/20210526193621.21559-1-catalin.marinas@arm.com
Will should have dropped the old one from linux-next but it takes a few
hours before Stephen re-creates the tree.
--
Catalin
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs
2021-05-26 21:48 ` Catalin Marinas
@ 2021-05-26 22:11 ` Jon Hunter
0 siblings, 0 replies; 13+ messages in thread
From: Jon Hunter @ 2021-05-26 22:11 UTC (permalink / raw)
To: Catalin Marinas
Cc: linux-arm-kernel, Will Deacon, Mark Rutland, Suzuki K Poulose,
linux-tegra
On 26/05/2021 22:48, Catalin Marinas wrote:
> On Wed, May 26, 2021 at 08:47:16PM +0100, Jon Hunter wrote:
>> On 11/05/2021 19:23, Catalin Marinas wrote:
>>> The GMID_EL1.BS field determines the number of tags accessed by the
>>> LDGM/STGM instructions (EL1 and up), used by the kernel for copying or
>>> zeroing page tags.
>>>
>>> Taint the kernel if GMID_EL1.BS differs between CPUs.
>>>
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
> [...]
>> I am seeing the following undefined instruction crash on all our
>> ARM64 Tegra devices on today's -next and bisect is pointing to
>> this patch. Reverting this patch on top of -next does fix the
>> problem. Let me know if you have any thoughts.
>
> Yeah, sorry about that. Posted a new version here, better tested:
>
> https://lore.kernel.org/r/20210526193621.21559-1-catalin.marinas@arm.com
>
> Will should have dropped the old one from linux-next but it takes a few
> hours before Stephen re-creates the tree.
No problem. Thanks for the quick fix!
Jon
--
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-05-26 22:14 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-11 18:23 [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Catalin Marinas
2021-05-11 18:23 ` [PATCH 1/2] arm64: Change the cpuinfo_arm64 member type for some sysregs to u64 Catalin Marinas
2021-05-12 13:29 ` Mark Rutland
2021-05-12 13:54 ` Suzuki K Poulose
2021-05-24 1:31 ` Shaokun Zhang
2021-05-26 16:07 ` Catalin Marinas
2021-05-11 18:23 ` [PATCH 2/2] arm64: Check if GMID_EL1.BS is the same on all CPUs Catalin Marinas
2021-05-12 13:33 ` Mark Rutland
2021-05-26 19:47 ` Jon Hunter
2021-05-26 21:08 ` Will Deacon
2021-05-26 21:48 ` Catalin Marinas
2021-05-26 22:11 ` Jon Hunter
2021-05-25 18:58 ` [PATCH 0/2] arm64: Taint the kernel on different GMID_EL1.BS Will Deacon
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